Search

Eric Coleman

Examiner (ID: 10499, Phone: (571)272-4163 , Office: P/2183 )

Most Active Art Unit
2183
Art Unit(s)
2183, 2783, 2302
Total Applications
2406
Issued Applications
2133
Pending Applications
59
Abandoned Applications
235

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10065624 [patent_doc_number] => 09104470 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-08-11 [patent_title] => 'Task processor' [patent_app_type] => utility [patent_app_number] => 14/243801 [patent_app_country] => US [patent_app_date] => 2014-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 26 [patent_no_of_words] => 23134 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14243801 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/243801
Task processor Apr 1, 2014 Issued
Array ( [id] => 10948546 [patent_doc_number] => 20140351565 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-11-27 [patent_title] => 'SYSTEM AND APPARATUS FOR GROUP FLOATING-POINT INFLATE AND DEFLATE OPERATIONS' [patent_app_type] => utility [patent_app_number] => 14/223741 [patent_app_country] => US [patent_app_date] => 2014-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 392 [patent_figures_cnt] => 392 [patent_no_of_words] => 81559 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14223741 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/223741
SYSTEM AND APPARATUS FOR GROUP FLOATING-POINT INFLATE AND DEFLATE OPERATIONS Mar 23, 2014 Abandoned
Array ( [id] => 10363290 [patent_doc_number] => 20150248295 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-09-03 [patent_title] => 'NUMERICAL STALL ANALYSIS OF CPU PERFORMANCE' [patent_app_type] => utility [patent_app_number] => 14/195783 [patent_app_country] => US [patent_app_date] => 2014-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5216 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14195783 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/195783
NUMERICAL STALL ANALYSIS OF CPU PERFORMANCE Mar 2, 2014 Abandoned
Array ( [id] => 10357208 [patent_doc_number] => 20150242213 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-08-27 [patent_title] => 'SYSTEM AND METHOD FOR MODIFICATION OF CODED INSTRUCTIONS IN READ-ONLY MEMORY USING ONE-TIME PROGRAMMABLE MEMORY' [patent_app_type] => utility [patent_app_number] => 14/187272 [patent_app_country] => US [patent_app_date] => 2014-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6920 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14187272 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/187272
SYSTEM AND METHOD FOR MODIFICATION OF CODED INSTRUCTIONS IN READ-ONLY MEMORY USING ONE-TIME PROGRAMMABLE MEMORY Feb 22, 2014 Abandoned
Array ( [id] => 11458880 [patent_doc_number] => 20170052786 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-02-23 [patent_title] => 'RECONFIGURABLE PROCESSOR AND CONDITIONAL EXECUTION METHOD FOR THE SAME' [patent_app_type] => utility [patent_app_number] => 15/119716 [patent_app_country] => US [patent_app_date] => 2014-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4897 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15119716 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/119716
Reconfigurable processor and conditional execution method for the same Feb 19, 2014 Issued
Array ( [id] => 10342363 [patent_doc_number] => 20150227368 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-08-13 [patent_title] => 'Completion Time Determination for Vector Instructions' [patent_app_type] => utility [patent_app_number] => 14/177378 [patent_app_country] => US [patent_app_date] => 2014-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 14804 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14177378 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/177378
Completion time determination for vector instructions Feb 10, 2014 Issued
Array ( [id] => 11359048 [patent_doc_number] => 09535701 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-01-03 [patent_title] => 'Efficient use of branch delay slots and branch prediction in pipelined computer architectures' [patent_app_type] => utility [patent_app_number] => 14/167973 [patent_app_country] => US [patent_app_date] => 2014-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 10691 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 350 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14167973 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/167973
Efficient use of branch delay slots and branch prediction in pipelined computer architectures Jan 28, 2014 Issued
Array ( [id] => 10327816 [patent_doc_number] => 20150212820 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-30 [patent_title] => 'PROCESSOR LOOP BUFFER' [patent_app_type] => utility [patent_app_number] => 14/164633 [patent_app_country] => US [patent_app_date] => 2014-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4957 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14164633 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/164633
Processor loop buffer Jan 26, 2014 Issued
Array ( [id] => 10575826 [patent_doc_number] => 09298467 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-03-29 [patent_title] => 'Switch statement prediction' [patent_app_type] => utility [patent_app_number] => 14/153188 [patent_app_country] => US [patent_app_date] => 2014-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 9523 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14153188 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/153188
Switch statement prediction Jan 12, 2014 Issued
Array ( [id] => 11482227 [patent_doc_number] => 09588773 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-03-07 [patent_title] => 'Software based application specific integrated circuit' [patent_app_type] => utility [patent_app_number] => 14/149009 [patent_app_country] => US [patent_app_date] => 2014-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 30 [patent_no_of_words] => 9300 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14149009 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/149009
Software based application specific integrated circuit Jan 6, 2014 Issued
Array ( [id] => 10065580 [patent_doc_number] => 09104425 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-08-11 [patent_title] => 'Apparatus and method for handling exception events' [patent_app_type] => utility [patent_app_number] => 14/149141 [patent_app_country] => US [patent_app_date] => 2014-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 10244 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14149141 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/149141
Apparatus and method for handling exception events Jan 6, 2014 Issued
Array ( [id] => 10556141 [patent_doc_number] => 09280341 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-03-08 [patent_title] => 'Data processing device' [patent_app_type] => utility [patent_app_number] => 14/144822 [patent_app_country] => US [patent_app_date] => 2013-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 8227 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14144822 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/144822
Data processing device Dec 30, 2013 Issued
Array ( [id] => 13820839 [patent_doc_number] => 10187208 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-22 [patent_title] => RSA algorithm acceleration processors, methods, systems, and instructions [patent_app_type] => utility [patent_app_number] => 15/102637 [patent_app_country] => US [patent_app_date] => 2013-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 16 [patent_no_of_words] => 14079 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15102637 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/102637
RSA algorithm acceleration processors, methods, systems, and instructions Dec 27, 2013 Issued
Array ( [id] => 11117027 [patent_doc_number] => 20160314000 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-27 [patent_title] => 'INSTRUCTION AND LOGIC FOR IDENTIFYING INSTRUCTIONS FOR RETIREMENT IN A MULTI-STRAND OUT-OF-ORDER PROCESSOR' [patent_app_type] => utility [patent_app_number] => 15/103765 [patent_app_country] => US [patent_app_date] => 2013-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 21047 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15103765 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/103765
Instruction and logic for identifying instructions for retirement in a multi-strand out-of-order processor Dec 22, 2013 Issued
Array ( [id] => 9398427 [patent_doc_number] => 20140095833 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-04-03 [patent_title] => 'Prefix Computer Instruction for Compatibly Extending Instruction Functionality' [patent_app_type] => utility [patent_app_number] => 14/100184 [patent_app_country] => US [patent_app_date] => 2013-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 21489 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14100184 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/100184
Prefix computer instruction for compatibly extending instruction functionality Dec 8, 2013 Issued
Array ( [id] => 9424120 [patent_doc_number] => 20140108771 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-04-17 [patent_title] => 'Using Register Last Use Information to Perform Decode Time Computer Instruction Optimization' [patent_app_type] => utility [patent_app_number] => 14/099313 [patent_app_country] => US [patent_app_date] => 2013-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 22529 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14099313 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/099313
Using register last use information to perform decode time computer instruction optimization Dec 5, 2013 Issued
Array ( [id] => 10873215 [patent_doc_number] => 08898435 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-11-25 [patent_title] => 'Optimizing system throughput by automatically altering thread co-execution based on operating system directives' [patent_app_type] => utility [patent_app_number] => 14/093340 [patent_app_country] => US [patent_app_date] => 2013-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7298 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14093340 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/093340
Optimizing system throughput by automatically altering thread co-execution based on operating system directives Nov 28, 2013 Issued
Array ( [id] => 9807898 [patent_doc_number] => 20150019843 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-01-15 [patent_title] => 'METHOD AND APPARATUS FOR SELECTIVE RENAMING IN A MICROPROCESSOR' [patent_app_type] => utility [patent_app_number] => 14/091340 [patent_app_country] => US [patent_app_date] => 2013-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9615 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14091340 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/091340
Method and apparatus for selective renaming in a microprocessor Nov 26, 2013 Issued
Array ( [id] => 9513222 [patent_doc_number] => 20140149714 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-29 [patent_title] => 'RECONFIGURABLE PROCESSOR FOR PARALLEL PROCESSING AND OPERATION METHOD OF THE RECONFIGURABLE PROCESSOR' [patent_app_type] => utility [patent_app_number] => 14/092060 [patent_app_country] => US [patent_app_date] => 2013-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5084 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14092060 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/092060
Reconfigurable processor for parallel processing and operation method of the reconfigurable processor Nov 26, 2013 Issued
Array ( [id] => 11238974 [patent_doc_number] => 09465619 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-10-11 [patent_title] => 'Systems and methods for shared pipeline architectures having minimalized delay' [patent_app_type] => utility [patent_app_number] => 14/090698 [patent_app_country] => US [patent_app_date] => 2013-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5685 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14090698 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/090698
Systems and methods for shared pipeline architectures having minimalized delay Nov 25, 2013 Issued
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