Search

Eric Coleman

Examiner (ID: 10499, Phone: (571)272-4163 , Office: P/2183 )

Most Active Art Unit
2183
Art Unit(s)
2183, 2783, 2302
Total Applications
2406
Issued Applications
2133
Pending Applications
59
Abandoned Applications
235

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11764273 [patent_doc_number] => 09372696 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-06-21 [patent_title] => 'Microprocessor with compressed and uncompressed microcode memories' [patent_app_type] => utility [patent_app_number] => 14/088620 [patent_app_country] => US [patent_app_date] => 2013-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 10853 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14088620 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/088620
Microprocessor with compressed and uncompressed microcode memories Nov 24, 2013 Issued
Array ( [id] => 10228260 [patent_doc_number] => 20150113253 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-23 [patent_title] => 'SELECTIVELY COMPRESSED MICROCODE' [patent_app_type] => utility [patent_app_number] => 14/088565 [patent_app_country] => US [patent_app_date] => 2013-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 10884 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14088565 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/088565
Selectively compressed microcode Nov 24, 2013 Issued
Array ( [id] => 10258081 [patent_doc_number] => 20150143078 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-21 [patent_title] => 'VECTOR PROCESSING ENGINES (VPEs) EMPLOYING A TAPPED-DELAY LINE(S) FOR PROVIDING PRECISION FILTER VECTOR PROCESSING OPERATIONS WITH REDUCED SAMPLE RE-FETCHING AND POWER CONSUMPTION, AND RELATED VECTOR PROCESSOR SYSTEMS AND METHODS' [patent_app_type] => utility [patent_app_number] => 14/082075 [patent_app_country] => US [patent_app_date] => 2013-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 45 [patent_figures_cnt] => 45 [patent_no_of_words] => 55925 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14082075 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/082075
Vector processing engines (VPEs) employing a tapped-delay line(s) for providing precision filter vector processing operations with reduced sample re-fetching and power consumption, and related vector processor systems and methods Nov 14, 2013 Issued
Array ( [id] => 11584727 [patent_doc_number] => 09639369 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-05-02 [patent_title] => 'Split register file for operands of different sizes' [patent_app_type] => utility [patent_app_number] => 14/076660 [patent_app_country] => US [patent_app_date] => 2013-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 6230 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14076660 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/076660
Split register file for operands of different sizes Nov 10, 2013 Issued
Array ( [id] => 10589514 [patent_doc_number] => 09311129 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-04-12 [patent_title] => 'Methods and systems for converting a related group of physical machines to virtual machines' [patent_app_type] => utility [patent_app_number] => 14/050317 [patent_app_country] => US [patent_app_date] => 2013-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6581 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14050317 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/050317
Methods and systems for converting a related group of physical machines to virtual machines Oct 8, 2013 Issued
Array ( [id] => 9308444 [patent_doc_number] => 20140047118 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-02-13 [patent_title] => 'OPTIMIZING RESOURCE CONFIGURATIONS' [patent_app_type] => utility [patent_app_number] => 14/042026 [patent_app_country] => US [patent_app_date] => 2013-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 13912 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14042026 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/042026
Optimizing resource configurations Sep 29, 2013 Issued
Array ( [id] => 10885770 [patent_doc_number] => 08910174 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-12-09 [patent_title] => 'Storage system' [patent_app_type] => utility [patent_app_number] => 14/023509 [patent_app_country] => US [patent_app_date] => 2013-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 11284 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14023509 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/023509
Storage system Sep 10, 2013 Issued
Array ( [id] => 9745684 [patent_doc_number] => 20140281403 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-18 [patent_title] => 'CHAINING BETWEEN EXPOSED VECTOR PIPELINES' [patent_app_type] => utility [patent_app_number] => 13/966408 [patent_app_country] => US [patent_app_date] => 2013-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9260 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13966408 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/966408
Chaining between exposed vector pipelines Aug 13, 2013 Issued
Array ( [id] => 9398351 [patent_doc_number] => 20140095757 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-04-03 [patent_title] => 'MICROCONTROLLER PROGRAMMABLE SYSTEM ON A CHIP WITH PROGRAMMABLE INTERCONNECT' [patent_app_type] => utility [patent_app_number] => 13/966028 [patent_app_country] => US [patent_app_date] => 2013-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 41 [patent_figures_cnt] => 41 [patent_no_of_words] => 18289 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13966028 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/966028
Microcontroller programmable system on a chip with programmable interconnect Aug 12, 2013 Issued
Array ( [id] => 11252011 [patent_doc_number] => 09477515 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-10-25 [patent_title] => 'Handling operating system (OS) transitions in an unbounded transactional memory (UTM) mode' [patent_app_type] => utility [patent_app_number] => 13/956495 [patent_app_country] => US [patent_app_date] => 2013-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 11430 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13956495 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/956495
Handling operating system (OS) transitions in an unbounded transactional memory (UTM) mode Jul 31, 2013 Issued
Array ( [id] => 11252011 [patent_doc_number] => 09477515 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-10-25 [patent_title] => 'Handling operating system (OS) transitions in an unbounded transactional memory (UTM) mode' [patent_app_type] => utility [patent_app_number] => 13/956495 [patent_app_country] => US [patent_app_date] => 2013-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 11430 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13956495 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/956495
Handling operating system (OS) transitions in an unbounded transactional memory (UTM) mode Jul 31, 2013 Issued
Array ( [id] => 9176389 [patent_doc_number] => 20130318374 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-28 [patent_title] => 'DISTRIBUTION OF TASKS AMONG ASYMMETRIC PROCESSING ELEMENTS' [patent_app_type] => utility [patent_app_number] => 13/954980 [patent_app_country] => US [patent_app_date] => 2013-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4989 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13954980 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/954980
Distribution of tasks among asymmetric processing elements Jul 30, 2013 Issued
Array ( [id] => 9282910 [patent_doc_number] => 20140032878 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-30 [patent_title] => 'SPLIT EMBEDDED DRAM PROCESSOR' [patent_app_type] => utility [patent_app_number] => 13/942541 [patent_app_country] => US [patent_app_date] => 2013-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 15338 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13942541 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/942541
SPLIT EMBEDDED DRAM PROCESSOR Jul 14, 2013 Abandoned
Array ( [id] => 10439186 [patent_doc_number] => 20150324199 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-11-12 [patent_title] => 'COMPUTER PROCESSOR AND SYSTEM WITHOUT AN ARITHMETIC AND LOGIC UNIT' [patent_app_type] => utility [patent_app_number] => 14/410127 [patent_app_country] => US [patent_app_date] => 2013-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6266 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14410127 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/410127
COMPUTER PROCESSOR AND SYSTEM WITHOUT AN ARITHMETIC AND LOGIC UNIT Jul 5, 2013 Abandoned
Array ( [id] => 9695652 [patent_doc_number] => 08826283 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-09-02 [patent_title] => 'Low overhead fault tolerance through hybrid checkpointing and replay' [patent_app_type] => utility [patent_app_number] => 13/926777 [patent_app_country] => US [patent_app_date] => 2013-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5581 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13926777 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/926777
Low overhead fault tolerance through hybrid checkpointing and replay Jun 24, 2013 Issued
Array ( [id] => 9109880 [patent_doc_number] => 20130283012 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-24 [patent_title] => 'Methods and Apparatus for Scalable Array Processor Interrupt Detection and Response' [patent_app_type] => utility [patent_app_number] => 13/916877 [patent_app_country] => US [patent_app_date] => 2013-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 13627 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13916877 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/916877
Methods and apparatus for scalable array processor interrupt detection and response Jun 12, 2013 Issued
Array ( [id] => 10052333 [patent_doc_number] => 09092212 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-07-28 [patent_title] => 'Processors' [patent_app_type] => utility [patent_app_number] => 13/914747 [patent_app_country] => US [patent_app_date] => 2013-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 7731 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13914747 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/914747
Processors Jun 10, 2013 Issued
Array ( [id] => 9586062 [patent_doc_number] => 08776073 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-07-08 [patent_title] => 'Task prioritization based on users\' interest' [patent_app_type] => utility [patent_app_number] => 13/899253 [patent_app_country] => US [patent_app_date] => 2013-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 5244 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13899253 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/899253
Task prioritization based on users' interest May 20, 2013 Issued
Array ( [id] => 9486757 [patent_doc_number] => 08732719 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-05-20 [patent_title] => 'Method and system for managing resource connections' [patent_app_type] => utility [patent_app_number] => 13/854667 [patent_app_country] => US [patent_app_date] => 2013-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9129 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13854667 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/854667
Method and system for managing resource connections Mar 31, 2013 Issued
Array ( [id] => 11264907 [patent_doc_number] => 09489204 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-11-08 [patent_title] => 'Method and apparatus for precalculating a direct branch partial target address during a misprediction correction process' [patent_app_type] => utility [patent_app_number] => 13/842835 [patent_app_country] => US [patent_app_date] => 2013-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5552 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13842835 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/842835
Method and apparatus for precalculating a direct branch partial target address during a misprediction correction process Mar 14, 2013 Issued
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