Search

Eric Coleman

Examiner (ID: 10499, Phone: (571)272-4163 , Office: P/2183 )

Most Active Art Unit
2183
Art Unit(s)
2183, 2783, 2302
Total Applications
2406
Issued Applications
2133
Pending Applications
59
Abandoned Applications
235

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10550231 [patent_doc_number] => 09274856 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-03-01 [patent_title] => 'Improving processor performance for instruction sequences that include barrier instructions' [patent_app_type] => utility [patent_app_number] => 13/687306 [patent_app_country] => US [patent_app_date] => 2012-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 11932 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13687306 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/687306
Improving processor performance for instruction sequences that include barrier instructions Nov 27, 2012 Issued
Array ( [id] => 8735486 [patent_doc_number] => 20130081055 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-03-28 [patent_title] => 'TASK PROCESSOR' [patent_app_type] => utility [patent_app_number] => 13/682633 [patent_app_country] => US [patent_app_date] => 2012-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 23147 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13682633 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/682633
Task processor Nov 19, 2012 Issued
Array ( [id] => 10556313 [patent_doc_number] => 09280513 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-03-08 [patent_title] => 'Matrix processor proxy systems and methods' [patent_app_type] => utility [patent_app_number] => 13/633848 [patent_app_country] => US [patent_app_date] => 2012-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 18 [patent_no_of_words] => 17635 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13633848 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/633848
Matrix processor proxy systems and methods Oct 1, 2012 Issued
Array ( [id] => 11791025 [patent_doc_number] => 09400650 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-07-26 [patent_title] => 'Read and write masks update instruction for vectorization of recursive computations over interdependent data' [patent_app_type] => utility [patent_app_number] => 13/630247 [patent_app_country] => US [patent_app_date] => 2012-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 18 [patent_no_of_words] => 11297 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13630247 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/630247
Read and write masks update instruction for vectorization of recursive computations over interdependent data Sep 27, 2012 Issued
Array ( [id] => 11465656 [patent_doc_number] => 09582287 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-02-28 [patent_title] => 'Processor having multiple cores, shared core extension logic, and shared core extension utilization instructions' [patent_app_type] => utility [patent_app_number] => 13/629460 [patent_app_country] => US [patent_app_date] => 2012-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 17 [patent_no_of_words] => 17651 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13629460 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/629460
Processor having multiple cores, shared core extension logic, and shared core extension utilization instructions Sep 26, 2012 Issued
Array ( [id] => 9023435 [patent_doc_number] => 08533432 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-09-10 [patent_title] => 'Cache and/or socket sensitive multi-processor cores breadth-first traversal' [patent_app_type] => utility [patent_app_number] => 13/629087 [patent_app_country] => US [patent_app_date] => 2012-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4920 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13629087 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/629087
Cache and/or socket sensitive multi-processor cores breadth-first traversal Sep 26, 2012 Issued
Array ( [id] => 8588452 [patent_doc_number] => 20130007273 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-03 [patent_title] => 'OPTIMIZING RESOURCE CONFIGURATIONS' [patent_app_type] => utility [patent_app_number] => 13/615175 [patent_app_country] => US [patent_app_date] => 2012-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 13804 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13615175 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/615175
Optimizing resource configurations Sep 12, 2012 Issued
Array ( [id] => 8568700 [patent_doc_number] => 20120331271 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-12-27 [patent_title] => 'COMPRESSED INSTRUCTION FORMAT' [patent_app_type] => utility [patent_app_number] => 13/607594 [patent_app_country] => US [patent_app_date] => 2012-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6542 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13607594 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/607594
Compressed instruction format Sep 6, 2012 Issued
Array ( [id] => 8524758 [patent_doc_number] => 20120324166 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-12-20 [patent_title] => 'COMPUTER-IMPLEMENTED METHOD OF PROCESSING RESOURCE MANAGEMENT' [patent_app_type] => utility [patent_app_number] => 13/599102 [patent_app_country] => US [patent_app_date] => 2012-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4798 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13599102 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/599102
Computer-implemented method of processing resource management Aug 29, 2012 Issued
Array ( [id] => 9378900 [patent_doc_number] => 08683182 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-03-25 [patent_title] => 'System and apparatus for group floating-point inflate and deflate operations' [patent_app_type] => utility [patent_app_number] => 13/493750 [patent_app_country] => US [patent_app_date] => 2012-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 384 [patent_figures_cnt] => 319 [patent_no_of_words] => 81594 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13493750 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/493750
System and apparatus for group floating-point inflate and deflate operations Jun 10, 2012 Issued
Array ( [id] => 9578818 [patent_doc_number] => 08769248 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-07-01 [patent_title] => 'System and apparatus for group floating-point inflate and deflate operations' [patent_app_type] => utility [patent_app_number] => 13/493738 [patent_app_country] => US [patent_app_date] => 2012-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 386 [patent_figures_cnt] => 320 [patent_no_of_words] => 81566 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13493738 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/493738
System and apparatus for group floating-point inflate and deflate operations Jun 10, 2012 Issued
Array ( [id] => 8419149 [patent_doc_number] => 20120246649 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-09-27 [patent_title] => 'Synchronizing Access To Resources In A Hybrid Computing Environment' [patent_app_type] => utility [patent_app_number] => 13/491850 [patent_app_country] => US [patent_app_date] => 2012-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 12767 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13491850 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/491850
Synchronizing access to resources in a hybrid computing environment Jun 7, 2012 Issued
Array ( [id] => 9062808 [patent_doc_number] => 08549261 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-01 [patent_title] => 'Parallel computing apparatus and parallel computing method' [patent_app_type] => utility [patent_app_number] => 13/459360 [patent_app_country] => US [patent_app_date] => 2012-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 13263 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13459360 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/459360
Parallel computing apparatus and parallel computing method Apr 29, 2012 Issued
Array ( [id] => 11390788 [patent_doc_number] => 09552032 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-01-24 [patent_title] => 'Branch prediction power reduction' [patent_app_type] => utility [patent_app_number] => 13/458542 [patent_app_country] => US [patent_app_date] => 2012-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 11029 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13458542 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/458542
Branch prediction power reduction Apr 26, 2012 Issued
Array ( [id] => 11806290 [patent_doc_number] => 09547358 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-01-17 [patent_title] => 'Branch prediction power reduction' [patent_app_type] => utility [patent_app_number] => 13/458513 [patent_app_country] => US [patent_app_date] => 2012-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 11030 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13458513 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/458513
Branch prediction power reduction Apr 26, 2012 Issued
Array ( [id] => 9820875 [patent_doc_number] => 08930678 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-01-06 [patent_title] => 'Instruction and logic to length decode X86 instructions' [patent_app_type] => utility [patent_app_number] => 13/457257 [patent_app_country] => US [patent_app_date] => 2012-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 11398 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13457257 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/457257
Instruction and logic to length decode X86 instructions Apr 25, 2012 Issued
Array ( [id] => 9123755 [patent_doc_number] => 20130290677 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-31 [patent_title] => 'EFFICIENT EXTRACTION OF EXECUTION SETS FROM FETCH SETS' [patent_app_type] => utility [patent_app_number] => 13/456495 [patent_app_country] => US [patent_app_date] => 2012-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4997 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13456495 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/456495
Efficient extraction of execution sets from fetch sets Apr 25, 2012 Issued
Array ( [id] => 8349182 [patent_doc_number] => 20120210102 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-08-16 [patent_title] => 'Obtaining And Releasing Hardware Threads Without Hypervisor Involvement' [patent_app_type] => utility [patent_app_number] => 13/452854 [patent_app_country] => US [patent_app_date] => 2012-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 9128 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13452854 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/452854
Obtaining and releasing hardware threads without hypervisor involvement Apr 20, 2012 Issued
Array ( [id] => 8349401 [patent_doc_number] => 20120210322 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-08-16 [patent_title] => 'METHODS FOR SINGLE-OWNER MULTI-CONSUMER WORK QUEUES FOR REPEATABLE TASKS' [patent_app_type] => utility [patent_app_number] => 13/452286 [patent_app_country] => US [patent_app_date] => 2012-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 6957 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13452286 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/452286
Methods for single-owner multi-consumer work queues for repeatable tasks Apr 19, 2012 Issued
Array ( [id] => 8337309 [patent_doc_number] => 20120204010 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-08-09 [patent_title] => 'NON-QUIESCING KEY SETTING FACILITY' [patent_app_type] => utility [patent_app_number] => 13/452248 [patent_app_country] => US [patent_app_date] => 2012-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 16383 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13452248 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/452248
Non-quiescing key setting facility Apr 19, 2012 Issued
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