Search

Eric Coleman

Examiner (ID: 10499, Phone: (571)272-4163 , Office: P/2183 )

Most Active Art Unit
2183
Art Unit(s)
2183, 2783, 2302
Total Applications
2406
Issued Applications
2133
Pending Applications
59
Abandoned Applications
235

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10124301 [patent_doc_number] => 09158660 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-10-13 [patent_title] => 'Controlling operation of a run-time instrumentation facility' [patent_app_type] => utility [patent_app_number] => 13/422546 [patent_app_country] => US [patent_app_date] => 2012-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 19 [patent_no_of_words] => 19395 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 246 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13422546 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/422546
Controlling operation of a run-time instrumentation facility Mar 15, 2012 Issued
Array ( [id] => 11226740 [patent_doc_number] => 09454462 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-09-27 [patent_title] => 'Run-time instrumentation monitoring for processor characteristic changes' [patent_app_type] => utility [patent_app_number] => 13/422542 [patent_app_country] => US [patent_app_date] => 2012-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 19878 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13422542 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/422542
Run-time instrumentation monitoring for processor characteristic changes Mar 15, 2012 Issued
Array ( [id] => 8716309 [patent_doc_number] => 08402462 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-03-19 [patent_title] => 'Detection and management of dynamic migration of virtual environments' [patent_app_type] => utility [patent_app_number] => 13/418677 [patent_app_country] => US [patent_app_date] => 2012-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 5035 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13418677 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/418677
Detection and management of dynamic migration of virtual environments Mar 12, 2012 Issued
Array ( [id] => 8923909 [patent_doc_number] => 08489858 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-07-16 [patent_title] => 'Methods and apparatus for scalable array processor interrupt detection and response' [patent_app_type] => utility [patent_app_number] => 13/417490 [patent_app_country] => US [patent_app_date] => 2012-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 28 [patent_no_of_words] => 13839 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13417490 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/417490
Methods and apparatus for scalable array processor interrupt detection and response Mar 11, 2012 Issued
Array ( [id] => 10072325 [patent_doc_number] => 09110683 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-08-18 [patent_title] => 'Predicting branches for vector partitioning loops when processing vector instructions' [patent_app_type] => utility [patent_app_number] => 13/414606 [patent_app_country] => US [patent_app_date] => 2012-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 13447 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 240 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13414606 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/414606
Predicting branches for vector partitioning loops when processing vector instructions Mar 6, 2012 Issued
Array ( [id] => 10098703 [patent_doc_number] => 09135014 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-09-15 [patent_title] => 'Data processing system with latency tolerance execution' [patent_app_type] => utility [patent_app_number] => 13/397452 [patent_app_country] => US [patent_app_date] => 2012-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9612 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 249 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13397452 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/397452
Data processing system with latency tolerance execution Feb 14, 2012 Issued
Array ( [id] => 10027663 [patent_doc_number] => 09069564 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-06-30 [patent_title] => 'Weighted instruction count scheduling' [patent_app_type] => utility [patent_app_number] => 13/396007 [patent_app_country] => US [patent_app_date] => 2012-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 5505 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13396007 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/396007
Weighted instruction count scheduling Feb 13, 2012 Issued
Array ( [id] => 8979155 [patent_doc_number] => 20130212585 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-15 [patent_title] => 'DATA PROCESSING SYSTEM OPERABLE IN SINGLE AND MULTI-THREAD MODES AND HAVING MULTIPLE CACHES AND METHOD OF OPERATION' [patent_app_type] => utility [patent_app_number] => 13/370420 [patent_app_country] => US [patent_app_date] => 2012-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 14602 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13370420 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/370420
Data processing system operable in single and multi-thread modes and having multiple caches and method of operation Feb 9, 2012 Issued
Array ( [id] => 8479159 [patent_doc_number] => 20120278565 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-01 [patent_title] => 'PROCESSING DEVICE, CONTROLLING UNIT, AND METHOD FOR PROCESSING' [patent_app_type] => utility [patent_app_number] => 13/369715 [patent_app_country] => US [patent_app_date] => 2012-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 12482 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13369715 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/369715
PROCESSING DEVICE, CONTROLLING UNIT, AND METHOD FOR PROCESSING Feb 8, 2012 Abandoned
Array ( [id] => 9826017 [patent_doc_number] => 08935513 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-01-13 [patent_title] => 'Processor performance improvement for instruction sequences that include barrier instructions' [patent_app_type] => utility [patent_app_number] => 13/369029 [patent_app_country] => US [patent_app_date] => 2012-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 11904 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13369029 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/369029
Processor performance improvement for instruction sequences that include barrier instructions Feb 7, 2012 Issued
Array ( [id] => 11801311 [patent_doc_number] => 09542187 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-01-10 [patent_title] => 'Guest instruction block with near branching and far branching sequence construction to native instruction block' [patent_app_type] => utility [patent_app_number] => 13/359817 [patent_app_country] => US [patent_app_date] => 2012-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 11397 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13359817 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/359817
Guest instruction block with near branching and far branching sequence construction to native instruction block Jan 26, 2012 Issued
Array ( [id] => 11523410 [patent_doc_number] => 09606808 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-03-28 [patent_title] => 'Method and system for resolving thread divergences' [patent_app_type] => utility [patent_app_number] => 13/348544 [patent_app_country] => US [patent_app_date] => 2012-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9146 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13348544 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/348544
Method and system for resolving thread divergences Jan 10, 2012 Issued
Array ( [id] => 8162631 [patent_doc_number] => 20120102301 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-04-26 [patent_title] => 'PREDICATE COUNT AND SEGMENT COUNT INSTRUCTIONS FOR PROCESSING VECTORS' [patent_app_type] => utility [patent_app_number] => 13/343619 [patent_app_country] => US [patent_app_date] => 2012-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 39557 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0102/20120102301.pdf [firstpage_image] =>[orig_patent_app_number] => 13343619 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/343619
Predicate count and segment count instructions for processing vectors Jan 3, 2012 Issued
Array ( [id] => 11232638 [patent_doc_number] => 09459866 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-10-04 [patent_title] => 'Vector frequency compress instruction' [patent_app_type] => utility [patent_app_number] => 13/993058 [patent_app_country] => US [patent_app_date] => 2011-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 23 [patent_no_of_words] => 16623 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13993058 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/993058
Vector frequency compress instruction Dec 29, 2011 Issued
Array ( [id] => 9213914 [patent_doc_number] => 20140013091 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-09 [patent_title] => 'CAUSING AN INTERRUPT BASED ON EVENT COUNT' [patent_app_type] => utility [patent_app_number] => 13/991878 [patent_app_country] => US [patent_app_date] => 2011-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5153 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13991878 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/991878
Causing an interrupt based on event count Dec 28, 2011 Issued
Array ( [id] => 9200353 [patent_doc_number] => 20130339668 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-12-19 [patent_title] => 'SYSTEMS, APPARATUSES, AND METHODS FOR PERFORMING DELTA DECODING ON PACKED DATA ELEMENTS' [patent_app_type] => utility [patent_app_number] => 13/997662 [patent_app_country] => US [patent_app_date] => 2011-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 16769 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13997662 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/997662
Systems, apparatuses, and methods for performing delta decoding on packed data elements Dec 27, 2011 Issued
Array ( [id] => 9465374 [patent_doc_number] => 20140129801 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-08 [patent_title] => 'SYSTEMS, APPARATUSES, AND METHODS FOR PERFORMING DELTA ENCODING ON PACKED DATA ELEMENTS' [patent_app_type] => utility [patent_app_number] => 13/976427 [patent_app_country] => US [patent_app_date] => 2011-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 16504 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13976427 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/976427
Systems, apparatuses, and methods for performing delta encoding on packed data elements Dec 27, 2011 Issued
Array ( [id] => 10962717 [patent_doc_number] => 20140365747 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-12-11 [patent_title] => 'SYSTEMS, APPARATUSES, AND METHODS FOR PERFORMING A HORIZONTAL PARTIAL SUM IN RESPONSE TO A SINGLE INSTRUCTION' [patent_app_type] => utility [patent_app_number] => 13/977612 [patent_app_country] => US [patent_app_date] => 2011-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 16884 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13977612 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/977612
Systems, apparatuses, and methods for performing a horizontal partial sum in response to a single instruction Dec 22, 2011 Issued
Array ( [id] => 11430961 [patent_doc_number] => 09569278 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-02-14 [patent_title] => 'Asymmetric performance multicore architecture with same instruction set architecture' [patent_app_type] => utility [patent_app_number] => 13/335257 [patent_app_country] => US [patent_app_date] => 2011-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3967 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13335257 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/335257
Asymmetric performance multicore architecture with same instruction set architecture Dec 21, 2011 Issued
Array ( [id] => 11563602 [patent_doc_number] => 09626191 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-04-18 [patent_title] => 'Shaped register file reads' [patent_app_type] => utility [patent_app_number] => 13/335868 [patent_app_country] => US [patent_app_date] => 2011-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9823 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13335868 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/335868
Shaped register file reads Dec 21, 2011 Issued
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