Search

Eric Coleman

Examiner (ID: 10499, Phone: (571)272-4163 , Office: P/2183 )

Most Active Art Unit
2183
Art Unit(s)
2183, 2783, 2302
Total Applications
2406
Issued Applications
2133
Pending Applications
59
Abandoned Applications
235

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8213881 [patent_doc_number] => 20120131310 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-24 [patent_title] => 'Methods And Apparatus For Independent Processor Node Operations In A SIMD Array Processor' [patent_app_type] => utility [patent_app_number] => 13/332482 [patent_app_country] => US [patent_app_date] => 2011-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4821 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0131/20120131310.pdf [firstpage_image] =>[orig_patent_app_number] => 13332482 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/332482
Methods and apparatus for independent processor node operations in a SIMD array processor Dec 20, 2011 Issued
Array ( [id] => 8267350 [patent_doc_number] => 20120166776 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-06-28 [patent_title] => 'METHOD, SYSTEM, AND COMPUTER PROGRAM FOR ANALYZING PROGRAM' [patent_app_type] => utility [patent_app_number] => 13/332436 [patent_app_country] => US [patent_app_date] => 2011-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 4689 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13332436 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/332436
Method, system, and computer program for analyzing program Dec 20, 2011 Issued
Array ( [id] => 9986454 [patent_doc_number] => 09032189 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-05-12 [patent_title] => 'Efficient conditional ALU instruction in read-port limited register file microprocessor' [patent_app_type] => utility [patent_app_number] => 13/333520 [patent_app_country] => US [patent_app_date] => 2011-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 36402 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13333520 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/333520
Efficient conditional ALU instruction in read-port limited register file microprocessor Dec 20, 2011 Issued
Array ( [id] => 9940712 [patent_doc_number] => 08990544 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-03-24 [patent_title] => 'Method and apparatus for using a previous column pointer to read entries in an array of a processor' [patent_app_type] => utility [patent_app_number] => 13/333125 [patent_app_country] => US [patent_app_date] => 2011-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 16 [patent_no_of_words] => 4396 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13333125 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/333125
Method and apparatus for using a previous column pointer to read entries in an array of a processor Dec 20, 2011 Issued
Array ( [id] => 10854147 [patent_doc_number] => 08880857 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-11-04 [patent_title] => 'Conditional ALU instruction pre-shift-generated carry flag propagation between microinstructions in read-port limited register file microprocessor' [patent_app_type] => utility [patent_app_number] => 13/333572 [patent_app_country] => US [patent_app_date] => 2011-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 36286 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 276 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13333572 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/333572
Conditional ALU instruction pre-shift-generated carry flag propagation between microinstructions in read-port limited register file microprocessor Dec 20, 2011 Issued
Array ( [id] => 9986451 [patent_doc_number] => 09032187 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-05-12 [patent_title] => 'Instruction execution' [patent_app_type] => utility [patent_app_number] => 13/331716 [patent_app_country] => US [patent_app_date] => 2011-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3652 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 239 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13331716 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/331716
Instruction execution Dec 19, 2011 Issued
Array ( [id] => 8568705 [patent_doc_number] => 20120331276 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-12-27 [patent_title] => 'Instruction Execution' [patent_app_type] => utility [patent_app_number] => 13/331828 [patent_app_country] => US [patent_app_date] => 2011-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4088 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13331828 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/331828
Instruction execution Dec 19, 2011 Issued
Array ( [id] => 8097857 [patent_doc_number] => 20120084533 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-04-05 [patent_title] => 'Efficient Parallel Floating Point Exception Handling In A Processor' [patent_app_type] => utility [patent_app_number] => 13/325559 [patent_app_country] => US [patent_app_date] => 2011-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9001 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0084/20120084533.pdf [firstpage_image] =>[orig_patent_app_number] => 13325559 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/325559
Efficient parallel floating point exception handling in a processor Dec 13, 2011 Issued
Array ( [id] => 10623489 [patent_doc_number] => 09342432 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-05-17 [patent_title] => 'Hardware performance-monitoring facility usage after context swaps' [patent_app_type] => utility [patent_app_number] => 13/313557 [patent_app_country] => US [patent_app_date] => 2011-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3172 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13313557 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/313557
Hardware performance-monitoring facility usage after context swaps Dec 6, 2011 Issued
Array ( [id] => 11193227 [patent_doc_number] => 09424042 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-08-23 [patent_title] => 'System, apparatus and method for translating vector instructions' [patent_app_type] => utility [patent_app_number] => 13/993603 [patent_app_country] => US [patent_app_date] => 2011-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 8901 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13993603 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/993603
System, apparatus and method for translating vector instructions Dec 5, 2011 Issued
Array ( [id] => 8337341 [patent_doc_number] => 20120204013 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-08-09 [patent_title] => 'SYSTEM AND APPARATUS FOR GROUP FLOATING-POINT ARITHMETIC OPERATIONS' [patent_app_type] => utility [patent_app_number] => 13/310508 [patent_app_country] => US [patent_app_date] => 2011-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 385 [patent_figures_cnt] => 385 [patent_no_of_words] => 81782 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13310508 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/310508
SYSTEM AND APPARATUS FOR GROUP FLOATING-POINT ARITHMETIC OPERATIONS Dec 1, 2011 Abandoned
Array ( [id] => 8985095 [patent_doc_number] => 08516225 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-08-20 [patent_title] => 'Central processing unit and microcontroller' [patent_app_type] => utility [patent_app_number] => 13/378482 [patent_app_country] => US [patent_app_date] => 2011-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5393 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13378482 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/378482
Central processing unit and microcontroller Nov 21, 2011 Issued
Array ( [id] => 8741128 [patent_doc_number] => 08412914 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-04-02 [patent_title] => 'Macroscalar processor architecture' [patent_app_type] => utility [patent_app_number] => 13/298739 [patent_app_country] => US [patent_app_date] => 2011-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 69 [patent_figures_cnt] => 95 [patent_no_of_words] => 38450 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13298739 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/298739
Macroscalar processor architecture Nov 16, 2011 Issued
Array ( [id] => 9257745 [patent_doc_number] => 08621186 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-12-31 [patent_title] => 'Obfuscated hardware multi-threading' [patent_app_type] => utility [patent_app_number] => 13/883937 [patent_app_country] => US [patent_app_date] => 2011-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5144 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13883937 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/883937
Obfuscated hardware multi-threading Nov 13, 2011 Issued
Array ( [id] => 8823781 [patent_doc_number] => 20130124826 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-16 [patent_title] => 'Optimizing System Throughput By Automatically Altering Thread Co-Execution Based On Operating System Directives' [patent_app_type] => utility [patent_app_number] => 13/294244 [patent_app_country] => US [patent_app_date] => 2011-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7263 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13294244 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/294244
Optimizing system throughput by automatically altering thread co-execution based on operating system directives Nov 10, 2011 Issued
Array ( [id] => 8823784 [patent_doc_number] => 20130124829 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-16 [patent_title] => 'REDUCING POWER CONSUMPTION AND RESOURCE UTILIZATION DURING MISS LOOKAHEAD' [patent_app_type] => utility [patent_app_number] => 13/293733 [patent_app_country] => US [patent_app_date] => 2011-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5691 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13293733 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/293733
Reducing power consumption and resource utilization during miss lookahead Nov 9, 2011 Issued
Array ( [id] => 8757034 [patent_doc_number] => 20130091339 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-04-11 [patent_title] => 'SIMD Memory Circuit And Methodology To Support Upsampling, Downsampling And Transposition' [patent_app_type] => utility [patent_app_number] => 13/253754 [patent_app_country] => US [patent_app_date] => 2011-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 10082 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13253754 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/253754
SIMD memory circuit and methodology to support upsampling, downsampling and transposition Oct 4, 2011 Issued
Array ( [id] => 8746644 [patent_doc_number] => 20130086361 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-04-04 [patent_title] => 'Scalable Decode-Time Instruction Sequence Optimization of Dependent Instructions' [patent_app_type] => utility [patent_app_number] => 13/251409 [patent_app_country] => US [patent_app_date] => 2011-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 13928 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13251409 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/251409
Scalable decode-time instruction sequence optimization of dependent instructions Oct 2, 2011 Issued
Array ( [id] => 8746651 [patent_doc_number] => 20130086368 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-04-04 [patent_title] => 'Using Register Last Use Infomation to Perform Decode-Time Computer Instruction Optimization' [patent_app_type] => utility [patent_app_number] => 13/251486 [patent_app_country] => US [patent_app_date] => 2011-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 22426 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13251486 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/251486
Using register last use infomation to perform decode-time computer instruction optimization Oct 2, 2011 Issued
Array ( [id] => 8746645 [patent_doc_number] => 20130086362 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-04-04 [patent_title] => 'Managing a Register Cache Based on an Architected Computer Instruction Set Having Operand First-Use Information' [patent_app_type] => utility [patent_app_number] => 13/251426 [patent_app_country] => US [patent_app_date] => 2011-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 21783 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13251426 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/251426
Prefix computer instruction for compatibily extending instruction functionality Oct 2, 2011 Issued
Menu