Search

Eric Coleman

Examiner (ID: 10499, Phone: (571)272-4163 , Office: P/2183 )

Most Active Art Unit
2183
Art Unit(s)
2183, 2783, 2302
Total Applications
2406
Issued Applications
2133
Pending Applications
59
Abandoned Applications
235

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8746643 [patent_doc_number] => 20130086360 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-04-04 [patent_title] => 'FIFO Load Instruction' [patent_app_type] => utility [patent_app_number] => 13/249284 [patent_app_country] => US [patent_app_date] => 2011-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5597 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13249284 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/249284
FIFO load instruction Sep 29, 2011 Issued
Array ( [id] => 9992617 [patent_doc_number] => 09037838 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-05-19 [patent_title] => 'Multiprocessor messaging system' [patent_app_type] => utility [patent_app_number] => 13/251151 [patent_app_country] => US [patent_app_date] => 2011-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2652 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13251151 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/251151
Multiprocessor messaging system Sep 29, 2011 Issued
Array ( [id] => 12495642 [patent_doc_number] => 09996499 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-06-12 [patent_title] => Scalable and programmable processor comprising multiple cooperating processor units [patent_app_type] => utility [patent_app_number] => 13/248869 [patent_app_country] => US [patent_app_date] => 2011-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8380 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13248869 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/248869
Scalable and programmable processor comprising multiple cooperating processor units Sep 28, 2011 Issued
Array ( [id] => 8619340 [patent_doc_number] => 20130024652 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-24 [patent_title] => 'Scalable Processing Unit' [patent_app_type] => utility [patent_app_number] => 13/236822 [patent_app_country] => US [patent_app_date] => 2011-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3191 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13236822 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/236822
Scalable processing unit Sep 19, 2011 Issued
Array ( [id] => 14034397 [patent_doc_number] => 10228949 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-03-12 [patent_title] => Single cycle multi-branch prediction including shadow cache for early far branch prediction [patent_app_type] => utility [patent_app_number] => 13/824013 [patent_app_country] => US [patent_app_date] => 2011-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4614 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13824013 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/824013
Single cycle multi-branch prediction including shadow cache for early far branch prediction Sep 15, 2011 Issued
Array ( [id] => 11889811 [patent_doc_number] => 09760372 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-09-12 [patent_title] => 'Parallel processing in plural processors with result register each performing associative operation on respective column data' [patent_app_type] => utility [patent_app_number] => 13/224090 [patent_app_country] => US [patent_app_date] => 2011-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 4751 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13224090 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/224090
Parallel processing in plural processors with result register each performing associative operation on respective column data Aug 31, 2011 Issued
Array ( [id] => 9781277 [patent_doc_number] => 08856498 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-10-07 [patent_title] => 'Prefetch request circuit' [patent_app_type] => utility [patent_app_number] => 13/220006 [patent_app_country] => US [patent_app_date] => 2011-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8399 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13220006 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/220006
Prefetch request circuit Aug 28, 2011 Issued
Array ( [id] => 7746843 [patent_doc_number] => 20120023311 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-01-26 [patent_title] => 'PROCESSOR APPARATUS AND MULTITHREAD PROCESSOR APPARATUS' [patent_app_type] => utility [patent_app_number] => 13/215623 [patent_app_country] => US [patent_app_date] => 2011-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 16237 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0023/20120023311.pdf [firstpage_image] =>[orig_patent_app_number] => 13215623 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/215623
Processor apparatus and multithread processor apparatus Aug 22, 2011 Issued
Array ( [id] => 8059453 [patent_doc_number] => 20120079458 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-29 [patent_title] => 'Debugging of a data processing apparatus' [patent_app_type] => utility [patent_app_number] => 13/137208 [patent_app_country] => US [patent_app_date] => 2011-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 11130 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0079/20120079458.pdf [firstpage_image] =>[orig_patent_app_number] => 13137208 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/137208
Debugging of a data processing apparatus Jul 27, 2011 Issued
Array ( [id] => 9077440 [patent_doc_number] => 08555033 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-08 [patent_title] => 'Extending operations of an application in a data processing system' [patent_app_type] => utility [patent_app_number] => 13/186556 [patent_app_country] => US [patent_app_date] => 2011-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 7302 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13186556 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/186556
Extending operations of an application in a data processing system Jul 19, 2011 Issued
Array ( [id] => 10556140 [patent_doc_number] => 09280342 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-03-08 [patent_title] => 'Vector operations for compressing selected vector elements' [patent_app_type] => utility [patent_app_number] => 13/187132 [patent_app_country] => US [patent_app_date] => 2011-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 6617 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13187132 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/187132
Vector operations for compressing selected vector elements Jul 19, 2011 Issued
Array ( [id] => 10078837 [patent_doc_number] => 09116685 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-08-25 [patent_title] => 'Table call instruction for frequently called functions' [patent_app_type] => utility [patent_app_number] => 13/185644 [patent_app_country] => US [patent_app_date] => 2011-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5373 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13185644 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/185644
Table call instruction for frequently called functions Jul 18, 2011 Issued
Array ( [id] => 9961223 [patent_doc_number] => 09009447 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-04-14 [patent_title] => 'Acceleration of string comparisons using vector instructions' [patent_app_type] => utility [patent_app_number] => 13/185244 [patent_app_country] => US [patent_app_date] => 2011-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 6630 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13185244 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/185244
Acceleration of string comparisons using vector instructions Jul 17, 2011 Issued
Array ( [id] => 9885918 [patent_doc_number] => 08972703 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-03-03 [patent_title] => 'Multithreaded processor architecture with operational latency hiding' [patent_app_type] => utility [patent_app_number] => 13/180724 [patent_app_country] => US [patent_app_date] => 2011-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 30 [patent_no_of_words] => 14715 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13180724 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/180724
Multithreaded processor architecture with operational latency hiding Jul 11, 2011 Issued
Array ( [id] => 7780598 [patent_doc_number] => 20120042154 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-02-16 [patent_title] => 'Illegal mode change handling' [patent_app_type] => utility [patent_app_number] => 13/067808 [patent_app_country] => US [patent_app_date] => 2011-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3711 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0042/20120042154.pdf [firstpage_image] =>[orig_patent_app_number] => 13067808 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/067808
Illegal mode change handling Jun 27, 2011 Issued
Array ( [id] => 9077441 [patent_doc_number] => 08555032 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-08 [patent_title] => 'Microcontroller programmable system on a chip with programmable interconnect' [patent_app_type] => utility [patent_app_number] => 13/169656 [patent_app_country] => US [patent_app_date] => 2011-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 36 [patent_no_of_words] => 18315 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13169656 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/169656
Microcontroller programmable system on a chip with programmable interconnect Jun 26, 2011 Issued
Array ( [id] => 9954359 [patent_doc_number] => 09003171 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-04-07 [patent_title] => 'Page fault prediction for processing vector instructions' [patent_app_type] => utility [patent_app_number] => 13/167630 [patent_app_country] => US [patent_app_date] => 2011-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 10690 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13167630 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/167630
Page fault prediction for processing vector instructions Jun 22, 2011 Issued
Array ( [id] => 10021234 [patent_doc_number] => 09063720 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-06-23 [patent_title] => 'Instruction and logic for processing text strings' [patent_app_type] => utility [patent_app_number] => 13/164715 [patent_app_country] => US [patent_app_date] => 2011-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 11694 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13164715 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/164715
Instruction and logic for processing text strings Jun 19, 2011 Issued
Array ( [id] => 9062813 [patent_doc_number] => 08549266 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-01 [patent_title] => 'System and method of instruction modification' [patent_app_type] => utility [patent_app_number] => 13/155291 [patent_app_country] => US [patent_app_date] => 2011-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 6342 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13155291 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/155291
System and method of instruction modification Jun 6, 2011 Issued
Array ( [id] => 8407847 [patent_doc_number] => 20120239914 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-09-20 [patent_title] => 'MULTITHREADED PARALLEL EXECUTION DEVICE, BROADCAST STREAM PLAYBACK DEVICE, BROADCAST STREAM STORAGE DEVICE, STORED STREAM PLAYBACK DEVICE, STORED STREAM RE-ENCODING DEVICE, INTEGRATED CIRCUIT, MULTITHREADED PARALLEL EXECUTION METHOD, AND MULTITHREADED COMPILER' [patent_app_type] => utility [patent_app_number] => 13/319848 [patent_app_country] => US [patent_app_date] => 2011-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 8826 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13319848 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/319848
Multithreaded parallel execution device, broadcast stream playback device, broadcast stream storage device, stored stream playback device, stored stream re-encoding device, integrated circuit, multithreaded parallel execution method, and multithreaded compiler Jun 2, 2011 Issued
Menu