Eric Coleman

Array ( [id] => 8222907 [patent_doc_number] => 20120137108 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-31 [patent_title] => 'SYSTEMS AND METHODS INTEGRATING BOOLEAN PROCESSING AND MEMORY' [patent_app_type] => utility [patent_app_number] => 13/114391 [patent_app_country] => US [patent_app_date] => 2011-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 15314 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13114391 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9187060 [patent_doc_number] => 08627046 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-01-07 [patent_title] => 'Data processing device' [patent_app_type] => utility [patent_app_number] => 13/113511 [patent_app_country] => US [patent_app_date] => 2011-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 8210 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13113511 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9578810 [patent_doc_number] => 08769245 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-07-01 [patent_title] => 'Very long instruction word (VLIW) processor with power management, and apparatus and method of power management therefor' [patent_app_type] => utility [patent_app_number] => 13/112307 [patent_app_country] => US [patent_app_date] => 2011-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 7958 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13112307 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10841191 [patent_doc_number] => 08868890 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-10-21 [patent_title] => 'No-delay microsequencer' [patent_app_type] => utility [patent_app_number] => 13/106119 [patent_app_country] => US [patent_app_date] => 2011-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6886 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13106119 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10901450 [patent_doc_number] => 08924693 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-12-30 [patent_title] => 'Predicting a result for a predicate-generating instruction when processing vector instructions' [patent_app_type] => utility [patent_app_number] => 13/106775 [patent_app_country] => US [patent_app_date] => 2011-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 12955 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13106775 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8491399 [patent_doc_number] => 20120290806 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-15 [patent_title] => 'SELECTIVE ROUTING OF LOCAL MEMORY ACCESSES AND DEVICE THEREOF' [patent_app_type] => utility [patent_app_number] => 13/103609 [patent_app_country] => US [patent_app_date] => 2011-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5935 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13103609 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9954355 [patent_doc_number] => 09003167 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-04-07 [patent_title] => 'Data processing apparatus and data processing method' [patent_app_type] => utility [patent_app_number] => 13/102168 [patent_app_country] => US [patent_app_date] => 2011-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 46 [patent_no_of_words] => 11875 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13102168 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10841187 [patent_doc_number] => 08868886 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-10-21 [patent_title] => 'Task switch immunized performance monitoring' [patent_app_type] => utility [patent_app_number] => 13/079189 [patent_app_country] => US [patent_app_date] => 2011-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3412 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13079189 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8432720 [patent_doc_number] => 20120254596 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-10-04 [patent_title] => 'METHOD AND SYSTEM FOR CONTROLLING MESSAGE TRAFFIC BETWEEN TWO PROCESSORS' [patent_app_type] => utility [patent_app_number] => 13/077689 [patent_app_country] => US [patent_app_date] => 2011-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5208 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13077689 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9967814 [patent_doc_number] => 09015449 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-04-21 [patent_title] => 'Region-weighted accounting of multi-threaded processor core according to dispatch state' [patent_app_type] => utility [patent_app_number] => 13/072716 [patent_app_country] => US [patent_app_date] => 2011-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8260 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13072716 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6104955 [patent_doc_number] => 20110167244 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-07-07 [patent_title] => 'EARLY INSTRUCTION TEXT BASED OPERAND STORE COMPARE REJECT AVOIDANCE' [patent_app_type] => utility [patent_app_number] => 13/050484 [patent_app_country] => US [patent_app_date] => 2011-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3100 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0167/20110167244.pdf [firstpage_image] =>[orig_patent_app_number] => 13050484 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9680470 [patent_doc_number] => 08819397 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-08-26 [patent_title] => 'Processor with increased efficiency via control word prediction' [patent_app_type] => utility [patent_app_number] => 13/037830 [patent_app_country] => US [patent_app_date] => 2011-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3352 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13037830 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9652142 [patent_doc_number] => 08806176 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-08-12 [patent_title] => 'Applying advanced energy manager in a distributed environment' [patent_app_type] => utility [patent_app_number] => 13/031915 [patent_app_country] => US [patent_app_date] => 2011-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 8544 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13031915 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6189268 [patent_doc_number] => 20110125984 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-05-26 [patent_title] => 'MICROPROCESSOR' [patent_app_type] => utility [patent_app_number] => 13/012001 [patent_app_country] => US [patent_app_date] => 2011-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3996 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0125/20110125984.pdf [firstpage_image] =>[orig_patent_app_number] => 13012001 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9665817 [patent_doc_number] => 08812825 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-08-19 [patent_title] => 'Methods and systems for managing performance and power utilization of a processor employing a fully multithreaded load threshold' [patent_app_type] => utility [patent_app_number] => 12/987591 [patent_app_country] => US [patent_app_date] => 2011-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5022 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12987591 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8280050 [patent_doc_number] => 20120173923 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-07-05 [patent_title] => 'ACCELERATING THE PERFORMANCE OF MATHEMATICAL FUNCTIONS IN HIGH PERFORMANCE COMPUTER SYSTEMS' [patent_app_type] => utility [patent_app_number] => 12/983092 [patent_app_country] => US [patent_app_date] => 2010-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4214 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12983092 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8279918 [patent_doc_number] => 20120173793 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-07-05 [patent_title] => 'MEMORY DEVICE USING EXTENDED INTERFACE COMMANDS' [patent_app_type] => utility [patent_app_number] => 12/982847 [patent_app_country] => US [patent_app_date] => 2010-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6644 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12982847 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9707325 [patent_doc_number] => 08832419 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-09-09 [patent_title] => 'Enhanced microcode address stack pointer manipulation' [patent_app_type] => utility [patent_app_number] => 12/978471 [patent_app_country] => US [patent_app_date] => 2010-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4354 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12978471 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9314905 [patent_doc_number] => 08656140 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-02-18 [patent_title] => 'Data processing device' [patent_app_type] => utility [patent_app_number] => 12/963072 [patent_app_country] => US [patent_app_date] => 2010-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6259 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 311 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12963072 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8202042 [patent_doc_number] => 20120124589 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-17 [patent_title] => 'MATRIX ALGORITHM FOR SCHEDULING OPERATIONS' [patent_app_type] => utility [patent_app_number] => 12/945432 [patent_app_country] => US [patent_app_date] => 2010-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8431 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0124/20120124589.pdf [firstpage_image] =>[orig_patent_app_number] => 12945432 [rel_patent_id] =>[rel_patent_doc_number] =>)