Eric Coleman

Array ( [id] => 4530426 [patent_doc_number] => 07913068 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-03-22 [patent_title] => 'System and method for providing asynchronous dynamic millicode entry prediction' [patent_app_type] => utility [patent_app_number] => 12/035109 [patent_app_country] => US [patent_app_date] => 2008-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3924 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/913/07913068.pdf [firstpage_image] =>[orig_patent_app_number] => 12035109 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4469941 [patent_doc_number] => 07882338 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-02-01 [patent_title] => 'Method, system and computer program product for an implicit predicted return from a predicted subroutine' [patent_app_type] => utility [patent_app_number] => 12/034066 [patent_app_country] => US [patent_app_date] => 2008-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3653 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/882/07882338.pdf [firstpage_image] =>[orig_patent_app_number] => 12034066 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5393371 [patent_doc_number] => 20090210684 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-20 [patent_title] => 'METHODS, SYSTEMS, AND COMPUTER PROGRAM PRODUCTS FOR RECOVERING FROM BRANCH PREDICTION LATENCY' [patent_app_type] => utility [patent_app_number] => 12/034112 [patent_app_country] => US [patent_app_date] => 2008-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4461 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0210/20090210684.pdf [firstpage_image] =>[orig_patent_app_number] => 12034112 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4590959 [patent_doc_number] => 07827390 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-02 [patent_title] => 'Microprocessor with private microcode RAM' [patent_app_type] => utility [patent_app_number] => 12/034503 [patent_app_country] => US [patent_app_date] => 2008-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 6136 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/827/07827390.pdf [firstpage_image] =>[orig_patent_app_number] => 12034503 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4530422 [patent_doc_number] => 07913067 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-03-22 [patent_title] => 'Method and system for overlapping execution of instructions through non-uniform execution pipelines in an in-order processor' [patent_app_type] => utility [patent_app_number] => 12/034084 [patent_app_country] => US [patent_app_date] => 2008-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4620 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/913/07913067.pdf [firstpage_image] =>[orig_patent_app_number] => 12034084 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5393362 [patent_doc_number] => 20090210675 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-20 [patent_title] => 'METHOD AND SYSTEM FOR EARLY INSTRUCTION TEXT BASED OPERAND STORE COMPARE REJECT AVOIDANCE' [patent_app_type] => utility [patent_app_number] => 12/034042 [patent_app_country] => US [patent_app_date] => 2008-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3065 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0210/20090210675.pdf [firstpage_image] =>[orig_patent_app_number] => 12034042 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4787678 [patent_doc_number] => 20080141007 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-12 [patent_title] => 'Boolean Processor' [patent_app_type] => utility [patent_app_number] => 12/033644 [patent_app_country] => US [patent_app_date] => 2008-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 15509 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0141/20080141007.pdf [firstpage_image] =>[orig_patent_app_number] => 12033644 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5393370 [patent_doc_number] => 20090210683 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-20 [patent_title] => 'METHOD AND APPARATUS FOR RECOVERING FROM BRANCH MISPREDICTION' [patent_app_type] => utility [patent_app_number] => 12/033626 [patent_app_country] => US [patent_app_date] => 2008-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3814 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0210/20090210683.pdf [firstpage_image] =>[orig_patent_app_number] => 12033626 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4830862 [patent_doc_number] => 20080127197 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-29 [patent_title] => 'METHOD AND SYSTEM FOR ON-DEMAND SCRATCH REGISTER RENAMING' [patent_app_type] => utility [patent_app_number] => 12/027665 [patent_app_country] => US [patent_app_date] => 2008-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3466 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0127/20080127197.pdf [firstpage_image] =>[orig_patent_app_number] => 12027665 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5437782 [patent_doc_number] => 20090172369 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-02 [patent_title] => 'SAVING AND RESTORING ARCHITECTURAL STATE FOR PROCESSOR CORES' [patent_app_type] => utility [patent_app_number] => 11/965167 [patent_app_country] => US [patent_app_date] => 2007-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7002 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0172/20090172369.pdf [firstpage_image] =>[orig_patent_app_number] => 11965167 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5437769 [patent_doc_number] => 20090172356 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-02 [patent_title] => 'COMPRESSED INSTRUCTION FORMAT' [patent_app_type] => utility [patent_app_number] => 11/965669 [patent_app_country] => US [patent_app_date] => 2007-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6526 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0172/20090172356.pdf [firstpage_image] =>[orig_patent_app_number] => 11965669 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4589836 [patent_doc_number] => 07831813 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-09 [patent_title] => 'Uses of known good code for implementing processor architectural modifications' [patent_app_type] => utility [patent_app_number] => 11/957848 [patent_app_country] => US [patent_app_date] => 2007-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 6988 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/831/07831813.pdf [firstpage_image] =>[orig_patent_app_number] => 11957848 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5548140 [patent_doc_number] => 20090158017 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-18 [patent_title] => 'TARGET-FREQUENCY BASED INDIRECT JUMP PREDICTION FOR HIGH-PERFORMANCE PROCESSORS' [patent_app_type] => utility [patent_app_number] => 11/957728 [patent_app_country] => US [patent_app_date] => 2007-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7756 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0158/20090158017.pdf [firstpage_image] =>[orig_patent_app_number] => 11957728 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5548133 [patent_doc_number] => 20090158010 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-18 [patent_title] => 'Command Protocol for Integrated Circuits' [patent_app_type] => utility [patent_app_number] => 11/955659 [patent_app_country] => US [patent_app_date] => 2007-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4626 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0158/20090158010.pdf [firstpage_image] =>[orig_patent_app_number] => 11955659 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4591963 [patent_doc_number] => 07836278 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-16 [patent_title] => 'Three operand instruction extension for X86 architecture' [patent_app_type] => utility [patent_app_number] => 11/954623 [patent_app_country] => US [patent_app_date] => 2007-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3692 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/836/07836278.pdf [firstpage_image] =>[orig_patent_app_number] => 11954623 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4787666 [patent_doc_number] => 20080140995 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-12 [patent_title] => 'Information processor and instruction fetch control method' [patent_app_type] => utility [patent_app_number] => 12/000164 [patent_app_country] => US [patent_app_date] => 2007-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 9047 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0140/20080140995.pdf [firstpage_image] =>[orig_patent_app_number] => 12000164 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5424191 [patent_doc_number] => 20090150647 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-11 [patent_title] => 'Processing Unit Incorporating Vectorizable Execution Unit' [patent_app_type] => utility [patent_app_number] => 11/952193 [patent_app_country] => US [patent_app_date] => 2007-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 10776 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0150/20090150647.pdf [firstpage_image] =>[orig_patent_app_number] => 11952193 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4641936 [patent_doc_number] => 08019970 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-09-13 [patent_title] => 'Three-dimensional networking design structure' [patent_app_type] => utility [patent_app_number] => 11/946422 [patent_app_country] => US [patent_app_date] => 2007-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 2549 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/019/08019970.pdf [firstpage_image] =>[orig_patent_app_number] => 11946422 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7972137 [patent_doc_number] => 07941647 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-05-10 [patent_title] => 'Computer for executing two instruction sets and adds a macroinstruction end marker for performing iterations after loop termination' [patent_app_type] => utility [patent_app_number] => 11/982419 [patent_app_country] => US [patent_app_date] => 2007-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 48 [patent_figures_cnt] => 61 [patent_no_of_words] => 88551 [patent_no_of_claims] => 54 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/941/07941647.pdf [firstpage_image] =>[orig_patent_app_number] => 11982419 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 28221 [patent_doc_number] => 07797512 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-09-14 [patent_title] => 'Virtual core management' [patent_app_type] => utility [patent_app_number] => 11/933297 [patent_app_country] => US [patent_app_date] => 2007-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 29 [patent_no_of_words] => 18779 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/797/07797512.pdf [firstpage_image] =>[orig_patent_app_number] => 11933297 [rel_patent_id] =>[rel_patent_doc_number] =>)