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Eric Coleman

Examiner (ID: 8960)

Most Active Art Unit
2183
Art Unit(s)
2183, 2302, 2783
Total Applications
2432
Issued Applications
2127
Pending Applications
100
Abandoned Applications
234

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19078593 [patent_doc_number] => 11947961 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-02 [patent_title] => Memory lookup computing mechanisms [patent_app_type] => utility [patent_app_number] => 18/060276 [patent_app_country] => US [patent_app_date] => 2022-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 5799 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18060276 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/060276
Memory lookup computing mechanisms Nov 29, 2022 Issued
Array ( [id] => 19045715 [patent_doc_number] => 11934828 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-03-19 [patent_title] => Performance management for accessing stored entities by multiple compute nodes of a storage system [patent_app_type] => utility [patent_app_number] => 18/059981 [patent_app_country] => US [patent_app_date] => 2022-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6565 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18059981 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/059981
Performance management for accessing stored entities by multiple compute nodes of a storage system Nov 28, 2022 Issued
Array ( [id] => 19198202 [patent_doc_number] => 11995441 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-05-28 [patent_title] => Instruction decoding using hash tables [patent_app_type] => utility [patent_app_number] => 17/985469 [patent_app_country] => US [patent_app_date] => 2022-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7300 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17985469 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/985469
Instruction decoding using hash tables Nov 10, 2022 Issued
Array ( [id] => 18897540 [patent_doc_number] => 20240013025 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-11 [patent_title] => CHIPLET-BASED HIERARCHICAL TREE TOPOLOGY ARCHITECTURE FOR NEUROMORPHIC COMPUTING [patent_app_type] => utility [patent_app_number] => 17/982995 [patent_app_country] => US [patent_app_date] => 2022-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5911 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17982995 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/982995
CHIPLET-BASED HIERARCHICAL TREE TOPOLOGY ARCHITECTURE FOR NEUROMORPHIC COMPUTING Nov 7, 2022 Pending
Array ( [id] => 18897540 [patent_doc_number] => 20240013025 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-11 [patent_title] => CHIPLET-BASED HIERARCHICAL TREE TOPOLOGY ARCHITECTURE FOR NEUROMORPHIC COMPUTING [patent_app_type] => utility [patent_app_number] => 17/982995 [patent_app_country] => US [patent_app_date] => 2022-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5911 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17982995 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/982995
CHIPLET-BASED HIERARCHICAL TREE TOPOLOGY ARCHITECTURE FOR NEUROMORPHIC COMPUTING Nov 7, 2022 Pending
Array ( [id] => 19078592 [patent_doc_number] => 11947960 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-02 [patent_title] => Modulo-space processing in multiply-and-accumulate units [patent_app_type] => utility [patent_app_number] => 18/052774 [patent_app_country] => US [patent_app_date] => 2022-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 10168 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18052774 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/052774
Modulo-space processing in multiply-and-accumulate units Nov 3, 2022 Issued
Array ( [id] => 18393374 [patent_doc_number] => 20230161594 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-25 [patent_title] => INSTRUCTION EXECUTION METHOD AND INSTRUCTION EXECUTION DEVICE [patent_app_type] => utility [patent_app_number] => 18/052909 [patent_app_country] => US [patent_app_date] => 2022-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10346 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18052909 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/052909
Instruction execution method and instruction execution device Nov 3, 2022 Issued
Array ( [id] => 18393373 [patent_doc_number] => 20230161593 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-25 [patent_title] => INSTRUCTION EXECUTION METHOD AND INSTRUCTION EXECUTION DEVICE [patent_app_type] => utility [patent_app_number] => 18/052908 [patent_app_country] => US [patent_app_date] => 2022-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10120 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18052908 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/052908
Instruction execution method and instruction execution device Nov 3, 2022 Issued
Array ( [id] => 19427180 [patent_doc_number] => 12086603 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-10 [patent_title] => Processor having multiple cores, shared core extension logic, and shared core extension utilization instructions [patent_app_type] => utility [patent_app_number] => 17/975596 [patent_app_country] => US [patent_app_date] => 2022-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 17 [patent_no_of_words] => 17274 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17975596 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/975596
Processor having multiple cores, shared core extension logic, and shared core extension utilization instructions Oct 26, 2022 Issued
Array ( [id] => 19167627 [patent_doc_number] => 11983536 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-05-14 [patent_title] => Instruction prefetch based power control [patent_app_type] => utility [patent_app_number] => 17/974314 [patent_app_country] => US [patent_app_date] => 2022-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 57 [patent_figures_cnt] => 59 [patent_no_of_words] => 78689 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17974314 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/974314
Instruction prefetch based power control Oct 25, 2022 Issued
Array ( [id] => 18393372 [patent_doc_number] => 20230161592 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-25 [patent_title] => Cooperative Instruction Prefetch on Multicore System [patent_app_type] => utility [patent_app_number] => 17/972681 [patent_app_country] => US [patent_app_date] => 2022-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6312 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17972681 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/972681
Cooperative instruction prefetch on multicore system Oct 24, 2022 Issued
Array ( [id] => 18207585 [patent_doc_number] => 20230053842 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-23 [patent_title] => STREAMING ENGINE WITH FLEXIBLE STREAMING ENGINE TEMPLATE SUPPORTING DIFFERING NUMBER OF NESTED LOOPS WITH CORRESPONDING LOOP COUNTS AND LOOP OFFSETS [patent_app_type] => utility [patent_app_number] => 17/972675 [patent_app_country] => US [patent_app_date] => 2022-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21316 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17972675 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/972675
Streaming engine with flexible streaming engine template supporting differing number of nested loops with corresponding loop counts and loop offsets Oct 24, 2022 Issued
Array ( [id] => 19122749 [patent_doc_number] => 11966738 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-23 [patent_title] => Processor and method for flushing translation lookaside buffer according to designated key identification code [patent_app_type] => utility [patent_app_number] => 18/046634 [patent_app_country] => US [patent_app_date] => 2022-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 6438 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18046634 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/046634
Processor and method for flushing translation lookaside buffer according to designated key identification code Oct 13, 2022 Issued
Array ( [id] => 19276477 [patent_doc_number] => 12026607 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-07-02 [patent_title] => Memory operation for systolic array [patent_app_type] => utility [patent_app_number] => 17/964291 [patent_app_country] => US [patent_app_date] => 2022-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 22617 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17964291 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/964291
Memory operation for systolic array Oct 11, 2022 Issued
Array ( [id] => 18998157 [patent_doc_number] => 11915005 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-02-27 [patent_title] => Branch predictor triggering [patent_app_type] => utility [patent_app_number] => 17/960390 [patent_app_country] => US [patent_app_date] => 2022-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 8817 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17960390 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/960390
Branch predictor triggering Oct 4, 2022 Issued
Array ( [id] => 18957361 [patent_doc_number] => 20240045688 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-08 [patent_title] => 8-BIT FLOATING POINT FUSED MULTIPLY INSTRUCTIONS [patent_app_type] => utility [patent_app_number] => 17/958369 [patent_app_country] => US [patent_app_date] => 2022-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16212 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -28 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17958369 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/958369
8-BIT FLOATING POINT FUSED MULTIPLY INSTRUCTIONS Sep 30, 2022 Pending
Array ( [id] => 18957356 [patent_doc_number] => 20240045683 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-08 [patent_title] => 8-BIT FLOATING POINT SQUARE ROOT AND/OR RECIPROCAL SQUARE ROOT INSTRUCTIONS [patent_app_type] => utility [patent_app_number] => 17/958371 [patent_app_country] => US [patent_app_date] => 2022-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14691 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17958371 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/958371
8-BIT FLOATING POINT SQUARE ROOT AND/OR RECIPROCAL SQUARE ROOT INSTRUCTIONS Sep 30, 2022 Pending
Array ( [id] => 18957362 [patent_doc_number] => 20240045689 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-08 [patent_title] => SYSTEMS AND METHODS FOR PERFORMING 8-BIT FLOATING-POINT VECTOR DOT PRODUCT INSTRUCTIONS [patent_app_type] => utility [patent_app_number] => 17/958377 [patent_app_country] => US [patent_app_date] => 2022-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14600 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17958377 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/958377
SYSTEMS AND METHODS FOR PERFORMING 8-BIT FLOATING-POINT VECTOR DOT PRODUCT INSTRUCTIONS Sep 30, 2022 Pending
Array ( [id] => 18957362 [patent_doc_number] => 20240045689 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-08 [patent_title] => SYSTEMS AND METHODS FOR PERFORMING 8-BIT FLOATING-POINT VECTOR DOT PRODUCT INSTRUCTIONS [patent_app_type] => utility [patent_app_number] => 17/958377 [patent_app_country] => US [patent_app_date] => 2022-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14600 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17958377 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/958377
SYSTEMS AND METHODS FOR PERFORMING 8-BIT FLOATING-POINT VECTOR DOT PRODUCT INSTRUCTIONS Sep 30, 2022 Pending
Array ( [id] => 19293612 [patent_doc_number] => 12032966 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-09 [patent_title] => Reducing overhead in processor array searching [patent_app_type] => utility [patent_app_number] => 17/958219 [patent_app_country] => US [patent_app_date] => 2022-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 7682 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17958219 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/958219
Reducing overhead in processor array searching Sep 29, 2022 Issued
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