Search

Eric Coleman

Examiner (ID: 10499, Phone: (571)272-4163 , Office: P/2183 )

Most Active Art Unit
2183
Art Unit(s)
2183, 2783, 2302
Total Applications
2406
Issued Applications
2133
Pending Applications
59
Abandoned Applications
235

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17869189 [patent_doc_number] => 20220291926 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-15 [patent_title] => SYSTEMS, METHODS, AND APPARATUSES FOR TILE STORE [patent_app_type] => utility [patent_app_number] => 17/706413 [patent_app_country] => US [patent_app_date] => 2022-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19036 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17706413 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/706413
Systems, methods, and apparatuses for tile store Mar 27, 2022 Issued
Array ( [id] => 17869190 [patent_doc_number] => 20220291927 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-15 [patent_title] => SYSTEMS, METHODS, AND APPARATUSES FOR TILE STORE [patent_app_type] => utility [patent_app_number] => 17/706428 [patent_app_country] => US [patent_app_date] => 2022-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19091 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17706428 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/706428
Systems, methods, and apparatuses for tile store Mar 27, 2022 Issued
Array ( [id] => 18694929 [patent_doc_number] => 20230325347 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-12 [patent_title] => General-Purpose Systolic Array [patent_app_type] => utility [patent_app_number] => 17/703479 [patent_app_country] => US [patent_app_date] => 2022-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8020 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17703479 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/703479
General-purpose systolic array Mar 23, 2022 Issued
Array ( [id] => 18687134 [patent_doc_number] => 11782871 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-10 [patent_title] => Method and apparatus for desynchronizing execution in a vector processor [patent_app_type] => utility [patent_app_number] => 17/701582 [patent_app_country] => US [patent_app_date] => 2022-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 10426 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17701582 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/701582
Method and apparatus for desynchronizing execution in a vector processor Mar 21, 2022 Issued
Array ( [id] => 18356824 [patent_doc_number] => 11645226 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-05-09 [patent_title] => Compiler operations for tensor streaming processor [patent_app_type] => utility [patent_app_number] => 17/697201 [patent_app_country] => US [patent_app_date] => 2022-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 11841 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17697201 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/697201
Compiler operations for tensor streaming processor Mar 16, 2022 Issued
Array ( [id] => 18687135 [patent_doc_number] => 11782872 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-10 [patent_title] => Distribution of over-configured logical processors [patent_app_type] => utility [patent_app_number] => 17/653798 [patent_app_country] => US [patent_app_date] => 2022-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 7627 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17653798 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/653798
Distribution of over-configured logical processors Mar 6, 2022 Issued
Array ( [id] => 18780778 [patent_doc_number] => 11822510 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-11-21 [patent_title] => Instruction format and instruction set architecture for tensor streaming processor [patent_app_type] => utility [patent_app_number] => 17/684337 [patent_app_country] => US [patent_app_date] => 2022-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 11876 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17684337 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/684337
Instruction format and instruction set architecture for tensor streaming processor Feb 28, 2022 Issued
Array ( [id] => 18415043 [patent_doc_number] => 11669586 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-06 [patent_title] => Systems and methods for combining low-mantissa units to achieve and exceed FP64 emulation of matrix multiplication [patent_app_type] => utility [patent_app_number] => 17/680483 [patent_app_country] => US [patent_app_date] => 2022-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 15718 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17680483 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/680483
Systems and methods for combining low-mantissa units to achieve and exceed FP64 emulation of matrix multiplication Feb 24, 2022 Issued
Array ( [id] => 17809411 [patent_doc_number] => 20220261246 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-18 [patent_title] => INSTRUCTION AND LOGIC FOR TRACKING FETCH PERFORMANCE BOTTLENECKS [patent_app_type] => utility [patent_app_number] => 17/675962 [patent_app_country] => US [patent_app_date] => 2022-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22864 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17675962 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/675962
Instruction and logic for tracking fetch performance bottlenecks Feb 17, 2022 Issued
Array ( [id] => 19522806 [patent_doc_number] => 12124530 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-22 [patent_title] => Computational memory [patent_app_type] => utility [patent_app_number] => 17/675729 [patent_app_country] => US [patent_app_date] => 2022-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 40 [patent_no_of_words] => 11308 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17675729 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/675729
Computational memory Feb 17, 2022 Issued
Array ( [id] => 19327929 [patent_doc_number] => 12045617 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-23 [patent_title] => Two-dimensional zero padding in a stream of matrix elements [patent_app_type] => utility [patent_app_number] => 17/670611 [patent_app_country] => US [patent_app_date] => 2022-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 49 [patent_no_of_words] => 36939 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17670611 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/670611
Two-dimensional zero padding in a stream of matrix elements Feb 13, 2022 Issued
Array ( [id] => 18553850 [patent_doc_number] => 20230251862 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-10 [patent_title] => MEMORY ACCESS OPERATIONS FOR LARGE GRAPH ANALYTICS [patent_app_type] => utility [patent_app_number] => 17/650620 [patent_app_country] => US [patent_app_date] => 2022-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8085 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17650620 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/650620
Memory access operations for large graph analytics Feb 9, 2022 Issued
Array ( [id] => 18414921 [patent_doc_number] => 11669463 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-06 [patent_title] => Method and apparatus for permuting streamed data elements [patent_app_type] => utility [patent_app_number] => 17/588416 [patent_app_country] => US [patent_app_date] => 2022-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 61 [patent_no_of_words] => 38673 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17588416 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/588416
Method and apparatus for permuting streamed data elements Jan 30, 2022 Issued
Array ( [id] => 18592145 [patent_doc_number] => 11741043 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-29 [patent_title] => Multi-core processing and memory arrangement [patent_app_type] => utility [patent_app_number] => 17/588168 [patent_app_country] => US [patent_app_date] => 2022-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4795 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17588168 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/588168
Multi-core processing and memory arrangement Jan 27, 2022 Issued
Array ( [id] => 18486961 [patent_doc_number] => 20230214307 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-06 [patent_title] => AUTOMATIC GENERATION OF COMPUTATION KERNELS FOR APPROXIMATING ELEMENTARY FUNCTIONS [patent_app_type] => utility [patent_app_number] => 17/569566 [patent_app_country] => US [patent_app_date] => 2022-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9861 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17569566 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/569566
Automatic generation of computation kernels for approximating elementary functions Jan 5, 2022 Issued
Array ( [id] => 18275993 [patent_doc_number] => 11614937 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-03-28 [patent_title] => Accelerator circuit for mathematical operations with immediate values table [patent_app_type] => utility [patent_app_number] => 17/566193 [patent_app_country] => US [patent_app_date] => 2021-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6798 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17566193 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/566193
Accelerator circuit for mathematical operations with immediate values table Dec 29, 2021 Issued
Array ( [id] => 18487006 [patent_doc_number] => 20230214352 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-06 [patent_title] => ISSUING INSTRUCTIONS ON A VECTOR PROCESSOR [patent_app_type] => utility [patent_app_number] => 17/566460 [patent_app_country] => US [patent_app_date] => 2021-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8563 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17566460 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/566460
Issuing instructions on a vector processor Dec 29, 2021 Issued
Array ( [id] => 18527648 [patent_doc_number] => 11714639 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-01 [patent_title] => Data processing device [patent_app_type] => utility [patent_app_number] => 17/565018 [patent_app_country] => US [patent_app_date] => 2021-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 8056 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17565018 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/565018
Data processing device Dec 28, 2021 Issued
Array ( [id] => 17736614 [patent_doc_number] => 20220222073 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-14 [patent_title] => PROCESSOR COMPRISING A DOUBLE MULTIPLICATION AND DOUBLE ADDITION OPERATOR ACTUABLE BY AN INSTRUCTION WITH THREE OPERAND REFERENCES [patent_app_type] => utility [patent_app_number] => 17/565120 [patent_app_country] => US [patent_app_date] => 2021-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4960 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17565120 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/565120
Processor comprising a double multiplication and double addition operator actuable by an instruction with three operand references Dec 28, 2021 Issued
Array ( [id] => 18471237 [patent_doc_number] => 20230205523 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-29 [patent_title] => HARDWARE DEVICE FOR ENFORCING ATOMICITY FOR MEMORY OPERATIONS [patent_app_type] => utility [patent_app_number] => 17/562853 [patent_app_country] => US [patent_app_date] => 2021-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6094 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17562853 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/562853
Hardware device for enforcing atomicity for memory operations Dec 26, 2021 Issued
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