Search

Eric D. Bertram

Examiner (ID: 10283, Phone: (571)272-3446 , Office: P/3766 )

Most Active Art Unit
3766
Art Unit(s)
3792, 3766, 3796, 3762
Total Applications
1515
Issued Applications
1125
Pending Applications
125
Abandoned Applications
295

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6571651 [patent_doc_number] => 20100320617 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-23 [patent_title] => 'METHODS TO MITIGATE PLASMA DAMAGE IN ORGANOSILICATE DIELECTRICS USING A PROTECTIVE SIDEWALL SPACER' [patent_app_type] => utility [patent_app_number] => 12/853354 [patent_app_country] => US [patent_app_date] => 2010-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9764 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0320/20100320617.pdf [firstpage_image] =>[orig_patent_app_number] => 12853354 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/853354
Methods to mitigate plasma damage in organosilicate dielectrics using a protective sidewall spacer Aug 9, 2010 Issued
Array ( [id] => 6020560 [patent_doc_number] => 20110049130 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-03 [patent_title] => 'SELF-REGULATING HEATER' [patent_app_type] => utility [patent_app_number] => 12/850954 [patent_app_country] => US [patent_app_date] => 2010-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4185 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0049/20110049130.pdf [firstpage_image] =>[orig_patent_app_number] => 12850954 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/850954
Self-regulating heater Aug 4, 2010 Issued
Array ( [id] => 6369032 [patent_doc_number] => 20100314729 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-16 [patent_title] => 'Stacked Chip Package Structure with Leadframe Having Inner Leads with Transfer Pad' [patent_app_type] => utility [patent_app_number] => 12/849188 [patent_app_country] => US [patent_app_date] => 2010-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 13280 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0314/20100314729.pdf [firstpage_image] =>[orig_patent_app_number] => 12849188 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/849188
Stacked chip package structure with leadframe having inner leads with transfer pad Aug 2, 2010 Issued
Array ( [id] => 6265565 [patent_doc_number] => 20100297841 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-11-25 [patent_title] => 'Method for providing a redistribution metal layer in an integrated circuit' [patent_app_type] => utility [patent_app_number] => 12/804870 [patent_app_country] => US [patent_app_date] => 2010-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4388 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0297/20100297841.pdf [firstpage_image] =>[orig_patent_app_number] => 12804870 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/804870
Method for providing a redistribution metal layer in an integrated circuit Jul 29, 2010 Issued
Array ( [id] => 8422277 [patent_doc_number] => 08278766 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-02 [patent_title] => 'Wafer level stack structure for system-in-package and method thereof' [patent_app_type] => utility [patent_app_number] => 12/805321 [patent_app_country] => US [patent_app_date] => 2010-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 4357 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12805321 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/805321
Wafer level stack structure for system-in-package and method thereof Jul 25, 2010 Issued
Array ( [id] => 9227757 [patent_doc_number] => 08633426 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-01-21 [patent_title] => 'Electrically heatable sheet of glass, method for production thereof and also window' [patent_app_type] => utility [patent_app_number] => 12/804472 [patent_app_country] => US [patent_app_date] => 2010-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5262 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12804472 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/804472
Electrically heatable sheet of glass, method for production thereof and also window Jul 21, 2010 Issued
Array ( [id] => 8270843 [patent_doc_number] => 08212347 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-07-03 [patent_title] => 'Stacked chip package structure with leadframe having bus bar' [patent_app_type] => utility [patent_app_number] => 12/827076 [patent_app_country] => US [patent_app_date] => 2010-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 27 [patent_no_of_words] => 5625 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12827076 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/827076
Stacked chip package structure with leadframe having bus bar Jun 29, 2010 Issued
Array ( [id] => 6231332 [patent_doc_number] => 20100264530 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-21 [patent_title] => 'Stacked Chip Package Structure with Leadframe Having Bus Bar' [patent_app_type] => utility [patent_app_number] => 12/827133 [patent_app_country] => US [patent_app_date] => 2010-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5619 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0264/20100264530.pdf [firstpage_image] =>[orig_patent_app_number] => 12827133 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/827133
Stacked chip package structure with leadframe having bus bar Jun 29, 2010 Issued
Array ( [id] => 8215029 [patent_doc_number] => 08193646 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-06-05 [patent_title] => 'Semiconductor component having through wire interconnect (TWI) with compressed wire' [patent_app_type] => utility [patent_app_number] => 12/824487 [patent_app_country] => US [patent_app_date] => 2010-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 55 [patent_no_of_words] => 12357 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/193/08193646.pdf [firstpage_image] =>[orig_patent_app_number] => 12824487 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/824487
Semiconductor component having through wire interconnect (TWI) with compressed wire Jun 27, 2010 Issued
Array ( [id] => 4624794 [patent_doc_number] => 08004095 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-08-23 [patent_title] => 'Semiconductor device and method of forming interconnect structure for encapsulated die having pre-applied protective layer' [patent_app_type] => utility [patent_app_number] => 12/822080 [patent_app_country] => US [patent_app_date] => 2010-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 16 [patent_no_of_words] => 3983 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/004/08004095.pdf [firstpage_image] =>[orig_patent_app_number] => 12822080 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/822080
Semiconductor device and method of forming interconnect structure for encapsulated die having pre-applied protective layer Jun 22, 2010 Issued
Array ( [id] => 6321428 [patent_doc_number] => 20100244245 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-30 [patent_title] => 'Filp Chip Interconnection Structure with Bump on Partial Pad and Method Thereof' [patent_app_type] => utility [patent_app_number] => 12/813335 [patent_app_country] => US [patent_app_date] => 2010-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3147 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0244/20100244245.pdf [firstpage_image] =>[orig_patent_app_number] => 12813335 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/813335
Filp chip interconnection structure with bump on partial pad and method thereof Jun 9, 2010 Issued
Array ( [id] => 8625507 [patent_doc_number] => 08358003 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-01-22 [patent_title] => 'Surface mount electronic device packaging assembly' [patent_app_type] => utility [patent_app_number] => 12/791545 [patent_app_country] => US [patent_app_date] => 2010-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 3770 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12791545 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/791545
Surface mount electronic device packaging assembly May 31, 2010 Issued
Array ( [id] => 9951078 [patent_doc_number] => 08999864 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-04-07 [patent_title] => 'Silicon wafer and method for heat-treating silicon wafer' [patent_app_type] => utility [patent_app_number] => 13/322080 [patent_app_country] => US [patent_app_date] => 2010-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 12784 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13322080 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/322080
Silicon wafer and method for heat-treating silicon wafer May 27, 2010 Issued
Array ( [id] => 6289380 [patent_doc_number] => 20100238632 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-23 [patent_title] => 'Load driving device' [patent_app_type] => utility [patent_app_number] => 12/801187 [patent_app_country] => US [patent_app_date] => 2010-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7731 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0238/20100238632.pdf [firstpage_image] =>[orig_patent_app_number] => 12801187 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/801187
Load driving device May 26, 2010 Issued
Array ( [id] => 9046746 [patent_doc_number] => 08541299 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-09-24 [patent_title] => 'Electrical interconnect forming method' [patent_app_type] => utility [patent_app_number] => 12/787527 [patent_app_country] => US [patent_app_date] => 2010-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 30 [patent_no_of_words] => 5999 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 446 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12787527 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/787527
Electrical interconnect forming method May 25, 2010 Issued
Array ( [id] => 6615092 [patent_doc_number] => 20100225008 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-09 [patent_title] => 'WIRE BOND INTERCONNECTION' [patent_app_type] => utility [patent_app_number] => 12/783039 [patent_app_country] => US [patent_app_date] => 2010-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5981 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0225/20100225008.pdf [firstpage_image] =>[orig_patent_app_number] => 12783039 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/783039
Wire bond interconnection May 18, 2010 Issued
Array ( [id] => 4483601 [patent_doc_number] => 07901998 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-03-08 [patent_title] => 'Packaging substrate having pattern-matched metal layers' [patent_app_type] => utility [patent_app_number] => 12/775970 [patent_app_country] => US [patent_app_date] => 2010-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 27 [patent_no_of_words] => 13541 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/901/07901998.pdf [firstpage_image] =>[orig_patent_app_number] => 12775970 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/775970
Packaging substrate having pattern-matched metal layers May 6, 2010 Issued
Array ( [id] => 6256348 [patent_doc_number] => 20100295184 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-11-25 [patent_title] => 'Method Of Manufacturing Semiconductor Device Including Wiring Layout And Semiconductor Device' [patent_app_type] => utility [patent_app_number] => 12/771067 [patent_app_country] => US [patent_app_date] => 2010-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3874 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0295/20100295184.pdf [firstpage_image] =>[orig_patent_app_number] => 12771067 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/771067
Method of manufacturing semiconductor device including wiring layout and semiconductor device Apr 29, 2010 Issued
Array ( [id] => 6153720 [patent_doc_number] => 20110156227 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-30 [patent_title] => 'SEMICONDUCTOR PACKAGE STRUCTURE' [patent_app_type] => utility [patent_app_number] => 12/770028 [patent_app_country] => US [patent_app_date] => 2010-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3904 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0156/20110156227.pdf [firstpage_image] =>[orig_patent_app_number] => 12770028 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/770028
Semiconductor package structure Apr 28, 2010 Issued
Array ( [id] => 7571011 [patent_doc_number] => 20110266667 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-11-03 [patent_title] => 'CU PILLAR BUMP WITH NON-METAL SIDEWALL PROTECTION STRUCTURE' [patent_app_type] => utility [patent_app_number] => 12/769768 [patent_app_country] => US [patent_app_date] => 2010-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5373 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0266/20110266667.pdf [firstpage_image] =>[orig_patent_app_number] => 12769768 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/769768
Cu pillar bump with non-metal sidewall protection structure Apr 28, 2010 Issued
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