Search

Eric D. Bertram

Examiner (ID: 10283)

Most Active Art Unit
3766
Art Unit(s)
3792, 3766, 3796, 3762
Total Applications
1976
Issued Applications
1684
Pending Applications
29
Abandoned Applications
273

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4849626 [patent_doc_number] => 20080315368 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-25 [patent_title] => 'Silicon Wafer Having Through-Wafer Vias' [patent_app_type] => utility [patent_app_number] => 12/202638 [patent_app_country] => US [patent_app_date] => 2008-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3560 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0315/20080315368.pdf [firstpage_image] =>[orig_patent_app_number] => 12202638 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/202638
Silicon wafer having through-wafer vias Sep 1, 2008 Issued
Array ( [id] => 8675385 [patent_doc_number] => 08383498 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-02-26 [patent_title] => 'Method for formation of tips' [patent_app_type] => utility [patent_app_number] => 12/675138 [patent_app_country] => US [patent_app_date] => 2008-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 5951 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12675138 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/675138
Method for formation of tips Aug 28, 2008 Issued
Array ( [id] => 4849675 [patent_doc_number] => 20080315417 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-25 [patent_title] => 'CHIP PACKAGE' [patent_app_type] => utility [patent_app_number] => 12/201231 [patent_app_country] => US [patent_app_date] => 2008-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2385 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0315/20080315417.pdf [firstpage_image] =>[orig_patent_app_number] => 12201231 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/201231
CHIP PACKAGE Aug 28, 2008 Abandoned
Array ( [id] => 4948664 [patent_doc_number] => 20080304790 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-11 [patent_title] => 'OPTICAL DEVICE AND METHOD FOR FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/191639 [patent_app_country] => US [patent_app_date] => 2008-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7716 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0304/20080304790.pdf [firstpage_image] =>[orig_patent_app_number] => 12191639 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/191639
Optical device and method for fabricating the same Aug 13, 2008 Issued
Array ( [id] => 141964 [patent_doc_number] => 07691745 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-04-06 [patent_title] => 'Land patterns for a semiconductor stacking structure and method therefor' [patent_app_type] => utility [patent_app_number] => 12/187578 [patent_app_country] => US [patent_app_date] => 2008-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2196 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/691/07691745.pdf [firstpage_image] =>[orig_patent_app_number] => 12187578 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/187578
Land patterns for a semiconductor stacking structure and method therefor Aug 6, 2008 Issued
Array ( [id] => 303973 [patent_doc_number] => 07535113 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-05-19 [patent_title] => 'Reduced inductance in ball grid array packages' [patent_app_type] => utility [patent_app_number] => 12/187092 [patent_app_country] => US [patent_app_date] => 2008-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 7284 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/535/07535113.pdf [firstpage_image] =>[orig_patent_app_number] => 12187092 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/187092
Reduced inductance in ball grid array packages Aug 5, 2008 Issued
Array ( [id] => 5449889 [patent_doc_number] => 20090065925 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-12 [patent_title] => 'DUAL-SIDED CHIP ATTACHED MODULES' [patent_app_type] => utility [patent_app_number] => 12/186655 [patent_app_country] => US [patent_app_date] => 2008-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4422 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0065/20090065925.pdf [firstpage_image] =>[orig_patent_app_number] => 12186655 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/186655
Dual-sided chip attached modules Aug 5, 2008 Issued
Array ( [id] => 4789528 [patent_doc_number] => 20080290501 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-27 [patent_title] => 'SEMICONDUCTOR PACKAGE' [patent_app_type] => utility [patent_app_number] => 12/184641 [patent_app_country] => US [patent_app_date] => 2008-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2859 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0290/20080290501.pdf [firstpage_image] =>[orig_patent_app_number] => 12184641 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/184641
Semiconductor package Jul 31, 2008 Issued
Array ( [id] => 4776033 [patent_doc_number] => 20080284031 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-20 [patent_title] => 'METHOD FOR IMPROVED PROCESS LATITUDE BY ELONGATED VIA INTEGRATION' [patent_app_type] => utility [patent_app_number] => 12/180882 [patent_app_country] => US [patent_app_date] => 2008-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2513 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0284/20080284031.pdf [firstpage_image] =>[orig_patent_app_number] => 12180882 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/180882
METHOD FOR IMPROVED PROCESS LATITUDE BY ELONGATED VIA INTEGRATION Jul 27, 2008 Abandoned
Array ( [id] => 112307 [patent_doc_number] => 07713790 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-05-11 [patent_title] => 'Method and system of tape automated bonding' [patent_app_type] => utility [patent_app_number] => 12/220711 [patent_app_country] => US [patent_app_date] => 2008-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 2901 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/713/07713790.pdf [firstpage_image] =>[orig_patent_app_number] => 12220711 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/220711
Method and system of tape automated bonding Jul 27, 2008 Issued
Array ( [id] => 4856541 [patent_doc_number] => 20080265391 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-30 [patent_title] => 'ETCHED INTERPOSER FOR INTEGRATED CIRCUIT DEVICES' [patent_app_type] => utility [patent_app_number] => 12/169542 [patent_app_country] => US [patent_app_date] => 2008-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5451 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0265/20080265391.pdf [firstpage_image] =>[orig_patent_app_number] => 12169542 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/169542
Etched interposer for integrated circuit devices Jul 7, 2008 Issued
Array ( [id] => 4469291 [patent_doc_number] => 07943435 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-05-17 [patent_title] => 'Underfill film having thermally conductive sheet' [patent_app_type] => utility [patent_app_number] => 12/164085 [patent_app_country] => US [patent_app_date] => 2008-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4436 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/943/07943435.pdf [firstpage_image] =>[orig_patent_app_number] => 12164085 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/164085
Underfill film having thermally conductive sheet Jun 28, 2008 Issued
Array ( [id] => 5441470 [patent_doc_number] => 20090093109 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-09 [patent_title] => 'Method for producing a semiconductor device using a solder alloy' [patent_app_type] => utility [patent_app_number] => 12/213923 [patent_app_country] => US [patent_app_date] => 2008-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3370 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0093/20090093109.pdf [firstpage_image] =>[orig_patent_app_number] => 12213923 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/213923
Method for producing a semiconductor device using a solder alloy Jun 25, 2008 Issued
Array ( [id] => 6321071 [patent_doc_number] => 20100244161 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-30 [patent_title] => 'WAFER LEVEL PACKAGING USING FLIP CHIP MOUNTING' [patent_app_type] => utility [patent_app_number] => 12/740922 [patent_app_country] => US [patent_app_date] => 2008-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6090 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0244/20100244161.pdf [firstpage_image] =>[orig_patent_app_number] => 12740922 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/740922
Wafer level packaging using flip chip mounting Jun 24, 2008 Issued
Array ( [id] => 9677574 [patent_doc_number] => 08816486 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-08-26 [patent_title] => 'Pad structure for 3D integrated circuit' [patent_app_type] => utility [patent_app_number] => 12/119255 [patent_app_country] => US [patent_app_date] => 2008-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 2369 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 392 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12119255 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/119255
Pad structure for 3D integrated circuit May 11, 2008 Issued
Array ( [id] => 6444100 [patent_doc_number] => 20100038354 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-02-18 [patent_title] => 'HEATING APPARATUS' [patent_app_type] => utility [patent_app_number] => 12/531866 [patent_app_country] => US [patent_app_date] => 2008-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2657 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0038/20100038354.pdf [firstpage_image] =>[orig_patent_app_number] => 12531866 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/531866
Heating apparatus Mar 13, 2008 Issued
Array ( [id] => 4695478 [patent_doc_number] => 20080217662 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-11 [patent_title] => 'Space-efficient package for laterally conducting device' [patent_app_type] => utility [patent_app_number] => 12/075814 [patent_app_country] => US [patent_app_date] => 2008-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4242 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0217/20080217662.pdf [firstpage_image] =>[orig_patent_app_number] => 12075814 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/075814
Space-efficient package for laterally conducting device Mar 13, 2008 Issued
Array ( [id] => 4749336 [patent_doc_number] => 20080157407 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-03 [patent_title] => 'THREE DIMENSIONAL IC DEVICE AND ALIGNMENT METHODS OF IC DEVICE SUBSTRATES' [patent_app_type] => utility [patent_app_number] => 12/048015 [patent_app_country] => US [patent_app_date] => 2008-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2426 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0157/20080157407.pdf [firstpage_image] =>[orig_patent_app_number] => 12048015 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/048015
Three dimensional IC device and alignment methods of IC device substrates Mar 12, 2008 Issued
Array ( [id] => 152449 [patent_doc_number] => 07683495 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-03-23 [patent_title] => 'Integrated circuit package substrate having configurable bond pads' [patent_app_type] => utility [patent_app_number] => 12/038502 [patent_app_country] => US [patent_app_date] => 2008-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 19 [patent_no_of_words] => 7169 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/683/07683495.pdf [firstpage_image] =>[orig_patent_app_number] => 12038502 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/038502
Integrated circuit package substrate having configurable bond pads Feb 26, 2008 Issued
Array ( [id] => 81557 [patent_doc_number] => 07745322 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-06-29 [patent_title] => 'Wire bond interconnection' [patent_app_type] => utility [patent_app_number] => 12/032159 [patent_app_country] => US [patent_app_date] => 2008-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 23 [patent_no_of_words] => 5967 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/745/07745322.pdf [firstpage_image] =>[orig_patent_app_number] => 12032159 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/032159
Wire bond interconnection Feb 14, 2008 Issued
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