Search

Eric D. Lee

Examiner (ID: 16720, Phone: (571)270-7098 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2851, 2825
Total Applications
750
Issued Applications
606
Pending Applications
38
Abandoned Applications
124

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19695356 [patent_doc_number] => 20250013901 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-09 [patent_title] => Low-Latency, High-Performance Hybrid Computing [patent_app_type] => utility [patent_app_number] => 18/776851 [patent_app_country] => US [patent_app_date] => 2024-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17917 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18776851 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/776851
Low-Latency, High-Performance Hybrid Computing Jul 17, 2024 Pending
Array ( [id] => 20388444 [patent_doc_number] => 12488172 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-02 [patent_title] => Optimized layout cell [patent_app_type] => utility [patent_app_number] => 18/772680 [patent_app_country] => US [patent_app_date] => 2024-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 3067 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18772680 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/772680
Optimized layout cell Jul 14, 2024 Issued
Array ( [id] => 20228679 [patent_doc_number] => 12417332 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-16 [patent_title] => Integrated circuit, system for and method of forming an integrated circuit [patent_app_type] => utility [patent_app_number] => 18/768895 [patent_app_country] => US [patent_app_date] => 2024-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 28 [patent_no_of_words] => 20496 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 254 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18768895 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/768895
Integrated circuit, system for and method of forming an integrated circuit Jul 9, 2024 Issued
Array ( [id] => 20228679 [patent_doc_number] => 12417332 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-16 [patent_title] => Integrated circuit, system for and method of forming an integrated circuit [patent_app_type] => utility [patent_app_number] => 18/768895 [patent_app_country] => US [patent_app_date] => 2024-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 28 [patent_no_of_words] => 20496 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 254 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18768895 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/768895
Integrated circuit, system for and method of forming an integrated circuit Jul 9, 2024 Issued
Array ( [id] => 19926333 [patent_doc_number] => 12300627 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2025-05-13 [patent_title] => Integrated circuit structures having a watermark [patent_app_type] => utility [patent_app_number] => 18/750377 [patent_app_country] => US [patent_app_date] => 2024-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 0 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18750377 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/750377
Integrated circuit structures having a watermark Jun 20, 2024 Issued
Array ( [id] => 19434912 [patent_doc_number] => 20240303410 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-12 [patent_title] => INTEGRATED CIRCUIT INCLUDING STANDARD CELL AND METHOD OF MANUFACTURING THE INTEGRATED CIRCUIT [patent_app_type] => utility [patent_app_number] => 18/670009 [patent_app_country] => US [patent_app_date] => 2024-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8254 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18670009 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/670009
INTEGRATED CIRCUIT INCLUDING STANDARD CELL AND METHOD OF MANUFACTURING THE INTEGRATED CIRCUIT May 20, 2024 Pending
Array ( [id] => 19434912 [patent_doc_number] => 20240303410 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-12 [patent_title] => INTEGRATED CIRCUIT INCLUDING STANDARD CELL AND METHOD OF MANUFACTURING THE INTEGRATED CIRCUIT [patent_app_type] => utility [patent_app_number] => 18/670009 [patent_app_country] => US [patent_app_date] => 2024-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8254 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18670009 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/670009
INTEGRATED CIRCUIT INCLUDING STANDARD CELL AND METHOD OF MANUFACTURING THE INTEGRATED CIRCUIT May 20, 2024 Pending
Array ( [id] => 19303919 [patent_doc_number] => 20240232499 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-11 [patent_title] => APPARATUS AND METHOD FOR GENERATING A PARAMETERIZED WAVEGUIDE OPTICAL ELEMENTS [patent_app_type] => utility [patent_app_number] => 18/444142 [patent_app_country] => US [patent_app_date] => 2024-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5698 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18444142 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/444142
Apparatus and method for generating a parameterized waveguide optical elements Feb 15, 2024 Issued
Array ( [id] => 19934125 [patent_doc_number] => 12307330 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-20 [patent_title] => Method, apparatus, terminal and storage medium for quantum topology graph optimization [patent_app_type] => utility [patent_app_number] => 18/434090 [patent_app_country] => US [patent_app_date] => 2024-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 47 [patent_no_of_words] => 51214 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 321 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18434090 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/434090
Method, apparatus, terminal and storage medium for quantum topology graph optimization Feb 5, 2024 Issued
Array ( [id] => 19347788 [patent_doc_number] => 20240256752 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-01 [patent_title] => METHOD FOR DESIGNING SEMICONDUCTOR BASED ON GROUPING MACRO CELLS [patent_app_type] => utility [patent_app_number] => 18/421870 [patent_app_country] => US [patent_app_date] => 2024-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16945 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18421870 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/421870
METHOD FOR DESIGNING SEMICONDUCTOR BASED ON GROUPING MACRO CELLS Jan 23, 2024 Abandoned
Array ( [id] => 19228660 [patent_doc_number] => 12008297 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-06-11 [patent_title] => Method for performing double clustering to evaluate placement of semiconductor devices [patent_app_type] => utility [patent_app_number] => 18/420110 [patent_app_country] => US [patent_app_date] => 2024-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 15468 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18420110 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/420110
Method for performing double clustering to evaluate placement of semiconductor devices Jan 22, 2024 Issued
Array ( [id] => 19581629 [patent_doc_number] => 12147747 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-11-19 [patent_title] => Area oriented logic synthesis [patent_app_type] => utility [patent_app_number] => 18/536064 [patent_app_country] => US [patent_app_date] => 2023-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 43 [patent_figures_cnt] => 43 [patent_no_of_words] => 37550 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18536064 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/536064
Area oriented logic synthesis Dec 10, 2023 Issued
Array ( [id] => 19183032 [patent_doc_number] => 11989624 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-05-21 [patent_title] => Method and apparatus for optimizing a qubit control signal, and quantum computer [patent_app_type] => utility [patent_app_number] => 18/500040 [patent_app_country] => US [patent_app_date] => 2023-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 7156 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18500040 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/500040
Method and apparatus for optimizing a qubit control signal, and quantum computer Oct 31, 2023 Issued
Array ( [id] => 19639062 [patent_doc_number] => 12169670 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-17 [patent_title] => Systems and methods for designing a module semiconductor product [patent_app_type] => utility [patent_app_number] => 18/479179 [patent_app_country] => US [patent_app_date] => 2023-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7209 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18479179 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/479179
Systems and methods for designing a module semiconductor product Oct 1, 2023 Issued
Array ( [id] => 19506865 [patent_doc_number] => 12118287 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-15 [patent_title] => Automatic generation of sub-cells for an analog integrated circuit [patent_app_type] => utility [patent_app_number] => 18/447916 [patent_app_country] => US [patent_app_date] => 2023-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 24 [patent_no_of_words] => 8546 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18447916 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/447916
Automatic generation of sub-cells for an analog integrated circuit Aug 9, 2023 Issued
Array ( [id] => 18904971 [patent_doc_number] => 20240020456 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-18 [patent_title] => System and Method for Improving Design Performance Through Placement of Functional and Spare Cells by Leveraging LDE Effect [patent_app_type] => utility [patent_app_number] => 18/361950 [patent_app_country] => US [patent_app_date] => 2023-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6629 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18361950 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/361950
System and method for improving design performance through placement of functional and spare cells by leveraging LDE effect Jul 30, 2023 Issued
Array ( [id] => 19678176 [patent_doc_number] => 12190037 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-07 [patent_title] => Multiple power domains using nano-sheet structures [patent_app_type] => utility [patent_app_number] => 18/361519 [patent_app_country] => US [patent_app_date] => 2023-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 18 [patent_no_of_words] => 11476 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18361519 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/361519
Multiple power domains using nano-sheet structures Jul 27, 2023 Issued
Array ( [id] => 19398802 [patent_doc_number] => 12073170 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-27 [patent_title] => Integrated circuit, system for and method of forming an integrated circuit [patent_app_type] => utility [patent_app_number] => 18/354423 [patent_app_country] => US [patent_app_date] => 2023-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 28 [patent_no_of_words] => 25744 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 333 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18354423 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/354423
Integrated circuit, system for and method of forming an integrated circuit Jul 17, 2023 Issued
Array ( [id] => 19443353 [patent_doc_number] => 12093621 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-17 [patent_title] => Detecting out-of-bounds violations in a hardware design using formal verification [patent_app_type] => utility [patent_app_number] => 18/202929 [patent_app_country] => US [patent_app_date] => 2023-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 13779 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18202929 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/202929
Detecting out-of-bounds violations in a hardware design using formal verification May 27, 2023 Issued
Array ( [id] => 19669738 [patent_doc_number] => 12182490 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-31 [patent_title] => Semiconductor design automation system and computing system including the same [patent_app_type] => utility [patent_app_number] => 18/316405 [patent_app_country] => US [patent_app_date] => 2023-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6238 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18316405 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/316405
Semiconductor design automation system and computing system including the same May 11, 2023 Issued
Menu