Search

Eric D. Lee

Examiner (ID: 17546)

Most Active Art Unit
2851
Art Unit(s)
2851, 2825
Total Applications
769
Issued Applications
617
Pending Applications
44
Abandoned Applications
124

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16994544 [patent_doc_number] => 20210232964 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-29 [patent_title] => Method and Apparatus for Evaluating Quantum Gate in Superconducting Circuit, Device and Storage Medium [patent_app_type] => utility [patent_app_number] => 17/210950 [patent_app_country] => US [patent_app_date] => 2021-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8514 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17210950 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/210950
Method and Apparatus for Evaluating Quantum Gate in Superconducting Circuit, Device and Storage Medium Mar 23, 2021 Abandoned
Array ( [id] => 17899563 [patent_doc_number] => 20220309225 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-29 [patent_title] => Metal Routing Techniques [patent_app_type] => utility [patent_app_number] => 17/209903 [patent_app_country] => US [patent_app_date] => 2021-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7961 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17209903 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/209903
Metal routing techniques Mar 22, 2021 Issued
Array ( [id] => 16935041 [patent_doc_number] => 20210200930 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-01 [patent_title] => METHOD FOR EVALUATING FAILURE-IN-TIME [patent_app_type] => utility [patent_app_number] => 17/204275 [patent_app_country] => US [patent_app_date] => 2021-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5287 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17204275 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/204275
Method for evaluating failure-in-time Mar 16, 2021 Issued
Array ( [id] => 18811156 [patent_doc_number] => 20230385492 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-30 [patent_title] => Method for reconstructing physical connection relationships of general EDA model layouts [patent_app_type] => utility [patent_app_number] => 18/249571 [patent_app_country] => US [patent_app_date] => 2021-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2940 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18249571 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/249571
Method for reconstructing physical connection relationships of general EDA model layouts Mar 15, 2021 Pending
Array ( [id] => 17871503 [patent_doc_number] => 20220294240 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-15 [patent_title] => POWER SOLUTION CRADLE DOCK [patent_app_type] => utility [patent_app_number] => 17/196834 [patent_app_country] => US [patent_app_date] => 2021-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6678 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17196834 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/196834
Power solution cradle dock Mar 8, 2021 Issued
Array ( [id] => 17699298 [patent_doc_number] => 11373027 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-06-28 [patent_title] => System and method for routing in an electronic circuit design [patent_app_type] => utility [patent_app_number] => 17/194589 [patent_app_country] => US [patent_app_date] => 2021-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4095 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17194589 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/194589
System and method for routing in an electronic circuit design Mar 7, 2021 Issued
Array ( [id] => 17438046 [patent_doc_number] => 11263381 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-03-01 [patent_title] => System and method for updating shapes associated with an electronic design [patent_app_type] => utility [patent_app_number] => 17/193357 [patent_app_country] => US [patent_app_date] => 2021-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 32 [patent_no_of_words] => 5970 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17193357 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/193357
System and method for updating shapes associated with an electronic design Mar 4, 2021 Issued
Array ( [id] => 18982154 [patent_doc_number] => 11907328 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-20 [patent_title] => Apparatus and method for generating efficient convolution [patent_app_type] => utility [patent_app_number] => 17/192469 [patent_app_country] => US [patent_app_date] => 2021-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3119 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17192469 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/192469
Apparatus and method for generating efficient convolution Mar 3, 2021 Issued
Array ( [id] => 17589835 [patent_doc_number] => 11328108 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-10 [patent_title] => Predicting die susceptible to early lifetime failure [patent_app_type] => utility [patent_app_number] => 17/189621 [patent_app_country] => US [patent_app_date] => 2021-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2719 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17189621 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/189621
Predicting die susceptible to early lifetime failure Mar 1, 2021 Issued
Array ( [id] => 17231240 [patent_doc_number] => 20210357797 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-18 [patent_title] => Low-Latency, High-Performance Hybrid Computing [patent_app_type] => utility [patent_app_number] => 17/184702 [patent_app_country] => US [patent_app_date] => 2021-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17892 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17184702 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/184702
Low-latency, high-performance hybrid computing Feb 24, 2021 Issued
Array ( [id] => 17054657 [patent_doc_number] => 20210264091 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-26 [patent_title] => SOURCE MASK OPTIMIZATION BY PROCESS DEFECTS PREDICTION [patent_app_type] => utility [patent_app_number] => 17/184521 [patent_app_country] => US [patent_app_date] => 2021-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5927 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17184521 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/184521
Source mask optimization by process defects prediction Feb 23, 2021 Issued
Array ( [id] => 19508030 [patent_doc_number] => 12119462 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-15 [patent_title] => Sensing device for detecting analytes in batteries [patent_app_type] => utility [patent_app_number] => 17/182082 [patent_app_country] => US [patent_app_date] => 2021-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 33 [patent_no_of_words] => 14381 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17182082 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/182082
Sensing device for detecting analytes in batteries Feb 21, 2021 Issued
Array ( [id] => 17347696 [patent_doc_number] => 20220014027 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-13 [patent_title] => APPARATUS FOR IMPROVING CELL BALANCING AND CELL FAILURE DETECTION [patent_app_type] => utility [patent_app_number] => 17/181968 [patent_app_country] => US [patent_app_date] => 2021-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7045 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17181968 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/181968
APPARATUS FOR IMPROVING CELL BALANCING AND CELL FAILURE DETECTION Feb 21, 2021 Abandoned
Array ( [id] => 17024428 [patent_doc_number] => 20210248300 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-12 [patent_title] => Systems and Methods for Improving Design Performance Through Placement of Functional and Spare Cells by Leveraging LDE Effect [patent_app_type] => utility [patent_app_number] => 17/179690 [patent_app_country] => US [patent_app_date] => 2021-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6541 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17179690 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/179690
Systems and methods for improving design performance through placement of functional and spare cells by leveraging LDE effect Feb 18, 2021 Issued
Array ( [id] => 17651740 [patent_doc_number] => 11354470 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-06-07 [patent_title] => System and method for device placement [patent_app_type] => utility [patent_app_number] => 17/173440 [patent_app_country] => US [patent_app_date] => 2021-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 5952 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17173440 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/173440
System and method for device placement Feb 10, 2021 Issued
Array ( [id] => 17515902 [patent_doc_number] => 11295057 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-04-05 [patent_title] => Continuous and discrete corner regularization in multi-PVT timing prediction [patent_app_type] => utility [patent_app_number] => 17/172200 [patent_app_country] => US [patent_app_date] => 2021-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 10636 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17172200 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/172200
Continuous and discrete corner regularization in multi-PVT timing prediction Feb 9, 2021 Issued
Array ( [id] => 16872475 [patent_doc_number] => 20210165942 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-03 [patent_title] => DETECTING OUT-OF-BOUNDS VIOLATIONS IN A HARDWARE DESIGN USING FORMAL VERIFICATION [patent_app_type] => utility [patent_app_number] => 17/168945 [patent_app_country] => US [patent_app_date] => 2021-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13738 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 268 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17168945 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/168945
Detecting out-of-bounds violations in a hardware design using formal verification Feb 4, 2021 Issued
Array ( [id] => 18243082 [patent_doc_number] => 20230075393 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-09 [patent_title] => APPARATUS, SYSTEMS AND METHODS FOR LOAD-ADAPTIVE 3D WIRELESS CHARGING [patent_app_type] => utility [patent_app_number] => 17/800316 [patent_app_country] => US [patent_app_date] => 2021-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14280 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -35 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17800316 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/800316
APPARATUS, SYSTEMS AND METHODS FOR LOAD-ADAPTIVE 3D WIRELESS CHARGING Feb 4, 2021 Pending
Array ( [id] => 17778971 [patent_doc_number] => 20220245321 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-04 [patent_title] => APPARATUS AND METHOD FOR GENERATING A PARAMETERIZED WAVEGUIDE OPTICAL ELEMENTS [patent_app_type] => utility [patent_app_number] => 17/162912 [patent_app_country] => US [patent_app_date] => 2021-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5628 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17162912 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/162912
Apparatus and method for generating a parameterized waveguide optical elements Jan 28, 2021 Issued
Array ( [id] => 17589839 [patent_doc_number] => 11328112 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-05-10 [patent_title] => Timing-aware testing [patent_app_type] => utility [patent_app_number] => 17/160192 [patent_app_country] => US [patent_app_date] => 2021-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4384 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17160192 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/160192
Timing-aware testing Jan 26, 2021 Issued
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