Search

Eric D. Lee

Examiner (ID: 1963, Phone: (571)270-7098 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2851, 2825
Total Applications
773
Issued Applications
618
Pending Applications
46
Abandoned Applications
125

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17955424 [patent_doc_number] => 11481533 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-25 [patent_title] => Systems and methods for designing a module semiconductor product [patent_app_type] => utility [patent_app_number] => 17/076072 [patent_app_country] => US [patent_app_date] => 2020-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7128 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 301 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17076072 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/076072
Systems and methods for designing a module semiconductor product Oct 20, 2020 Issued
Array ( [id] => 17365224 [patent_doc_number] => 11232247 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-01-25 [patent_title] => Adaptable dynamic region for hardware acceleration [patent_app_type] => utility [patent_app_number] => 17/075364 [patent_app_country] => US [patent_app_date] => 2020-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 14554 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17075364 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/075364
Adaptable dynamic region for hardware acceleration Oct 19, 2020 Issued
Array ( [id] => 18023254 [patent_doc_number] => 20220374753 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-24 [patent_title] => QUANTUM GATE AND QUANTUM COMPUTER [patent_app_type] => utility [patent_app_number] => 17/769715 [patent_app_country] => US [patent_app_date] => 2020-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14385 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 31 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17769715 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/769715
Quantum gate and quantum computer Oct 15, 2020 Issued
Array ( [id] => 18031033 [patent_doc_number] => 11514223 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-29 [patent_title] => Systems and methods to extract qubit parameters [patent_app_type] => utility [patent_app_number] => 17/068388 [patent_app_country] => US [patent_app_date] => 2020-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6231 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17068388 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/068388
Systems and methods to extract qubit parameters Oct 11, 2020 Issued
Array ( [id] => 18357036 [patent_doc_number] => 11645440 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-05-09 [patent_title] => Machine learning based delay estimation [patent_app_type] => utility [patent_app_number] => 17/062324 [patent_app_country] => US [patent_app_date] => 2020-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7624 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17062324 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/062324
Machine learning based delay estimation Oct 1, 2020 Issued
Array ( [id] => 18031027 [patent_doc_number] => 11514217 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-29 [patent_title] => Systems and methods for generating ethernet modules based on base designs [patent_app_type] => utility [patent_app_number] => 17/035654 [patent_app_country] => US [patent_app_date] => 2020-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 20313 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17035654 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/035654
Systems and methods for generating ethernet modules based on base designs Sep 27, 2020 Issued
Array ( [id] => 16722552 [patent_doc_number] => 20210089699 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-25 [patent_title] => SEAMLESS TRANSITION BETWEEN ROUTING MODES [patent_app_type] => utility [patent_app_number] => 17/026114 [patent_app_country] => US [patent_app_date] => 2020-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6142 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17026114 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/026114
Seamless transition between routing modes Sep 17, 2020 Issued
Array ( [id] => 17325591 [patent_doc_number] => 11216605 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-01-04 [patent_title] => Interactive system for guiding electronics design and assembly [patent_app_type] => utility [patent_app_number] => 17/024567 [patent_app_country] => US [patent_app_date] => 2020-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 13500 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17024567 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/024567
Interactive system for guiding electronics design and assembly Sep 16, 2020 Issued
Array ( [id] => 20204388 [patent_doc_number] => 12407176 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-02 [patent_title] => Battery management apparatus [patent_app_type] => utility [patent_app_number] => 17/637883 [patent_app_country] => US [patent_app_date] => 2020-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 3460 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17637883 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/637883
Battery management apparatus Sep 15, 2020 Issued
Array ( [id] => 16545723 [patent_doc_number] => 20200412138 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-31 [patent_title] => SECONDARY BATTERY PROTECTION APPARATUS [patent_app_type] => utility [patent_app_number] => 17/016469 [patent_app_country] => US [patent_app_date] => 2020-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9398 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 524 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17016469 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/016469
Secondary battery protection apparatus Sep 9, 2020 Issued
Array ( [id] => 16676044 [patent_doc_number] => 20210064810 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-04 [patent_title] => Method to Perform Hardware Safety Analysis without Fault Simulation [patent_app_type] => utility [patent_app_number] => 17/011204 [patent_app_country] => US [patent_app_date] => 2020-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3612 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17011204 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/011204
Method to perform hardware safety analysis without fault simulation Sep 2, 2020 Issued
Array ( [id] => 16637182 [patent_doc_number] => 10915693 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-09 [patent_title] => System and method for implementing verification IP for pre-silicon functional verification of a layered protocol [patent_app_type] => utility [patent_app_number] => 17/010643 [patent_app_country] => US [patent_app_date] => 2020-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8402 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 489 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17010643 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/010643
System and method for implementing verification IP for pre-silicon functional verification of a layered protocol Sep 1, 2020 Issued
Array ( [id] => 18577950 [patent_doc_number] => 11734483 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-22 [patent_title] => Method of driving design on gate electrodes, and device and electronic device thereof [patent_app_type] => utility [patent_app_number] => 17/048596 [patent_app_country] => US [patent_app_date] => 2020-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 12055 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17048596 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/048596
Method of driving design on gate electrodes, and device and electronic device thereof Aug 11, 2020 Issued
Array ( [id] => 16751682 [patent_doc_number] => 20210103693 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-08 [patent_title] => DYNAMIC FREQUENCY BOOSTING IN INTEGRATED CIRCUITS [patent_app_type] => utility [patent_app_number] => 16/990975 [patent_app_country] => US [patent_app_date] => 2020-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9699 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16990975 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/990975
DYNAMIC FREQUENCY BOOSTING IN INTEGRATED CIRCUITS Aug 10, 2020 Abandoned
Array ( [id] => 16601977 [patent_doc_number] => 20210028508 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-28 [patent_title] => METHOD FOR DISCHARGING ELECTRICAL STORAGE DEVICES [patent_app_type] => utility [patent_app_number] => 16/940307 [patent_app_country] => US [patent_app_date] => 2020-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1828 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16940307 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/940307
METHOD FOR DISCHARGING ELECTRICAL STORAGE DEVICES Jul 26, 2020 Abandoned
Array ( [id] => 16424115 [patent_doc_number] => 20200349313 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-05 [patent_title] => DETECTING OUT-OF-BOUNDS VIOLATIONS IN A HARDWARE DESIGN USING FORMAL VERIFICATION [patent_app_type] => utility [patent_app_number] => 16/930424 [patent_app_country] => US [patent_app_date] => 2020-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13703 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 248 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16930424 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/930424
Detecting out-of-bounds violations in a hardware design using formal verification Jul 15, 2020 Issued
Array ( [id] => 16758859 [patent_doc_number] => 10977411 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-04-13 [patent_title] => Method for generating packing solution of printed circuit board [patent_app_type] => utility [patent_app_number] => 16/929656 [patent_app_country] => US [patent_app_date] => 2020-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 3539 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16929656 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/929656
Method for generating packing solution of printed circuit board Jul 14, 2020 Issued
Array ( [id] => 18918361 [patent_doc_number] => 11880641 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-23 [patent_title] => Pixel design method, pixel design device, and electronic equipment [patent_app_type] => utility [patent_app_number] => 16/968388 [patent_app_country] => US [patent_app_date] => 2020-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 11827 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16968388 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/968388
Pixel design method, pixel design device, and electronic equipment Jul 13, 2020 Issued
Array ( [id] => 19838724 [patent_doc_number] => 12251075 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-18 [patent_title] => Robot cleaner [patent_app_type] => utility [patent_app_number] => 17/597368 [patent_app_country] => US [patent_app_date] => 2020-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5738 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17597368 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/597368
Robot cleaner Jul 1, 2020 Issued
Array ( [id] => 16880227 [patent_doc_number] => 11030377 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-06-08 [patent_title] => Routing based on pin placement within routing blockage [patent_app_type] => utility [patent_app_number] => 16/895847 [patent_app_country] => US [patent_app_date] => 2020-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 10171 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 249 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16895847 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/895847
Routing based on pin placement within routing blockage Jun 7, 2020 Issued
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