Search

Eric D. Lee

Examiner (ID: 1963, Phone: (571)270-7098 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2851, 2825
Total Applications
773
Issued Applications
618
Pending Applications
46
Abandoned Applications
125

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17276852 [patent_doc_number] => 20210383050 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-09 [patent_title] => Circuit Layout Techniques [patent_app_type] => utility [patent_app_number] => 16/893378 [patent_app_country] => US [patent_app_date] => 2020-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7081 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16893378 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/893378
Circuit layout techniques Jun 3, 2020 Issued
Array ( [id] => 16508404 [patent_doc_number] => 20200387660 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-10 [patent_title] => MASK RULE CHECKING FOR CURVILINEAR MASKS FOR ELECTRONIC CIRCUITS [patent_app_type] => utility [patent_app_number] => 16/892252 [patent_app_country] => US [patent_app_date] => 2020-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12347 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16892252 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/892252
Mask rule checking for curvilinear masks for electronic circuits Jun 2, 2020 Issued
Array ( [id] => 16486585 [patent_doc_number] => 20200380192 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-03 [patent_title] => AUTOMATED CIRCUIT GENERATION [patent_app_type] => utility [patent_app_number] => 16/886577 [patent_app_country] => US [patent_app_date] => 2020-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 64563 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16886577 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/886577
Automated circuit generation May 27, 2020 Issued
Array ( [id] => 16300067 [patent_doc_number] => 20200285790 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-10 [patent_title] => METHOD AND APPARATUS FOR OBTAINING MATCHING PROCESS RESULTS AMONG MULTIPLE REACTION CHAMBERS [patent_app_type] => utility [patent_app_number] => 16/883766 [patent_app_country] => US [patent_app_date] => 2020-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4262 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16883766 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/883766
Method and apparatus for obtaining matching process results among multiple reaction chambers May 25, 2020 Issued
Array ( [id] => 16745466 [patent_doc_number] => 10970456 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-04-06 [patent_title] => Identifying root cause of layout versus schematic errors [patent_app_type] => utility [patent_app_number] => 16/878590 [patent_app_country] => US [patent_app_date] => 2020-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 5065 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16878590 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/878590
Identifying root cause of layout versus schematic errors May 18, 2020 Issued
Array ( [id] => 16286210 [patent_doc_number] => 20200279812 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-03 [patent_title] => POWER GRID, IC AND METHOD FOR PLACING POWER GRID [patent_app_type] => utility [patent_app_number] => 16/875060 [patent_app_country] => US [patent_app_date] => 2020-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7580 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16875060 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/875060
Power grid, IC and method for placing power grid May 14, 2020 Issued
Array ( [id] => 18889921 [patent_doc_number] => 11868694 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-01-09 [patent_title] => System and method for optimizing emulation throughput by selective application of a clock pattern [patent_app_type] => utility [patent_app_number] => 16/874197 [patent_app_country] => US [patent_app_date] => 2020-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 9514 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16874197 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/874197
System and method for optimizing emulation throughput by selective application of a clock pattern May 13, 2020 Issued
Array ( [id] => 18334928 [patent_doc_number] => 20230126876 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-27 [patent_title] => METHOD, DEVICE, AND ELECTRONIC APPARATUS OF INSPECTING DISPLAY PANEL [patent_app_type] => utility [patent_app_number] => 16/969566 [patent_app_country] => US [patent_app_date] => 2020-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7320 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16969566 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/969566
Method, device, and electronic apparatus of inspecting display panel May 12, 2020 Issued
Array ( [id] => 18235270 [patent_doc_number] => 11599829 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-03-07 [patent_title] => Free-form integration of machine learning model primitives [patent_app_type] => utility [patent_app_number] => 16/861671 [patent_app_country] => US [patent_app_date] => 2020-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 9874 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16861671 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/861671
Free-form integration of machine learning model primitives Apr 28, 2020 Issued
Array ( [id] => 16242118 [patent_doc_number] => 20200259352 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-13 [patent_title] => REGULATOR WITH HIGH SPEED NONLINEAR COMPENSATION [patent_app_type] => utility [patent_app_number] => 16/859925 [patent_app_country] => US [patent_app_date] => 2020-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9021 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16859925 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/859925
Regulator with high speed nonlinear compensation Apr 26, 2020 Issued
Array ( [id] => 18607075 [patent_doc_number] => 11748543 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-05 [patent_title] => Multiple power domains using nano-sheet structures [patent_app_type] => utility [patent_app_number] => 16/859459 [patent_app_country] => US [patent_app_date] => 2020-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 18 [patent_no_of_words] => 11441 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16859459 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/859459
Multiple power domains using nano-sheet structures Apr 26, 2020 Issued
Array ( [id] => 16300071 [patent_doc_number] => 20200285794 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-10 [patent_title] => TIMING ANALYSIS FOR PARALLEL MULTI-STATE DRIVER CIRCUITS [patent_app_type] => utility [patent_app_number] => 16/840634 [patent_app_country] => US [patent_app_date] => 2020-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7375 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16840634 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/840634
Timing analysis for parallel multi-state driver circuits Apr 5, 2020 Issued
Array ( [id] => 17802358 [patent_doc_number] => 11416659 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-08-16 [patent_title] => Implementing an asymmetric memory with random port ratios using dedicated memory primitives [patent_app_type] => utility [patent_app_number] => 16/834797 [patent_app_country] => US [patent_app_date] => 2020-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 18 [patent_no_of_words] => 11255 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16834797 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/834797
Implementing an asymmetric memory with random port ratios using dedicated memory primitives Mar 29, 2020 Issued
Array ( [id] => 17129280 [patent_doc_number] => 20210304049 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-30 [patent_title] => SYSTEM ARCHITECTURE AND METHODS OF DETERMINING DEVICE BEHAVIOR [patent_app_type] => utility [patent_app_number] => 16/829809 [patent_app_country] => US [patent_app_date] => 2020-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3181 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16829809 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/829809
System architecture and methods of determining device behavior Mar 24, 2020 Issued
Array ( [id] => 16316867 [patent_doc_number] => 20200295605 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-17 [patent_title] => DECODER FOR WIRELESS CHARGING TRANSMITTER AND WIRELESS CHARGING TRANSMITTER USING THE SAME [patent_app_type] => utility [patent_app_number] => 16/818285 [patent_app_country] => US [patent_app_date] => 2020-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6064 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16818285 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/818285
Decoder for wireless charging transmitter and wireless charging transmitter using the same Mar 12, 2020 Issued
Array ( [id] => 16271195 [patent_doc_number] => 20200272683 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-27 [patent_title] => METHOD AND SYSTEM FOR SOLVING THE LAGRANGIAN DUAL OF A CONSTRAINED BINARY QUADRATIC PROGRAMMING PROBLEM USING A QUANTUM ANNEALER [patent_app_type] => utility [patent_app_number] => 16/809473 [patent_app_country] => US [patent_app_date] => 2020-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8781 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16809473 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/809473
Method and system for solving the Lagrangian dual of a constrained binary quadratic programming problem using a quantum annealer Mar 3, 2020 Issued
Array ( [id] => 17062246 [patent_doc_number] => 11106851 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-08-31 [patent_title] => Serialization in electronic design automation flows [patent_app_type] => utility [patent_app_number] => 16/805604 [patent_app_country] => US [patent_app_date] => 2020-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4657 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16805604 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/805604
Serialization in electronic design automation flows Feb 27, 2020 Issued
Array ( [id] => 17121353 [patent_doc_number] => 11132489 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-09-28 [patent_title] => Layer assignment based on wirelength threshold [patent_app_type] => utility [patent_app_number] => 16/805155 [patent_app_country] => US [patent_app_date] => 2020-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8750 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16805155 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/805155
Layer assignment based on wirelength threshold Feb 27, 2020 Issued
Array ( [id] => 17523346 [patent_doc_number] => 20220109195 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-07 [patent_title] => PACK BATTERY CHARGING METHOD, PACK BATTERY, AND POWER SOURCE DEVICE [patent_app_type] => utility [patent_app_number] => 17/429327 [patent_app_country] => US [patent_app_date] => 2020-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4814 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17429327 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/429327
Pack battery charging method, pack battery, and power source device Feb 17, 2020 Issued
Array ( [id] => 17024427 [patent_doc_number] => 20210248299 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-12 [patent_title] => MACHINE LEARNING-BASED CLASSIFICATION IN PARASITIC EXTRACTION AUTOMATION FOR CIRCUIT DESIGN AND VERIFICATION [patent_app_type] => utility [patent_app_number] => 16/788545 [patent_app_country] => US [patent_app_date] => 2020-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8936 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16788545 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/788545
Machine learning-based classification in parasitic extraction automation for circuit design and verification Feb 11, 2020 Issued
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