Search

Eric D. Lee

Examiner (ID: 1963, Phone: (571)270-7098 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2851, 2825
Total Applications
773
Issued Applications
618
Pending Applications
46
Abandoned Applications
125

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 15045775 [patent_doc_number] => 20190333892 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-31 [patent_title] => REDUNDANCY SCHEME FOR A 3D STACKED DEVICE [patent_app_type] => utility [patent_app_number] => 15/967109 [patent_app_country] => US [patent_app_date] => 2018-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6342 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15967109 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/967109
Redundancy scheme for a 3D stacked device Apr 29, 2018 Issued
Array ( [id] => 13360137 [patent_doc_number] => 20180231608 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-16 [patent_title] => SYSTEMS AND METHODS FOR WAFER-LEVEL LOOPBACK TEST [patent_app_type] => utility [patent_app_number] => 15/955013 [patent_app_country] => US [patent_app_date] => 2018-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5854 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15955013 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/955013
Systems and methods for wafer-level loopback test Apr 16, 2018 Issued
Array ( [id] => 17096241 [patent_doc_number] => 20210284032 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-16 [patent_title] => CONTACTLESS MOTOR VEHICLE-CHARGING DEVICE, COMPONENT OF A CONTACTLESS MOTOR VEHICLE-CHARGING DEVICE, METHOD FOR CONTROLLING A CONTACTLESS MOTOR VEHICLE-CHARGING DEVICE AND A MOTOR VEHICLE HAVING A CONTACTLESS MOTOR VEHICLE-CHARGING DEVICE [patent_app_type] => utility [patent_app_number] => 16/613292 [patent_app_country] => US [patent_app_date] => 2018-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5313 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16613292 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/613292
Contactless motor vehicle-charging device, component of a contactless motor vehicle-charging device, method for controlling a contactless motor vehicle-charging device and a motor vehicle having a contactless motor vehicle-charging device Apr 15, 2018 Issued
Array ( [id] => 15526213 [patent_doc_number] => 20200055412 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-20 [patent_title] => CIRCUIT AND CHARGING METHOD FOR AN ELECTRICAL ENERGY STORAGE SYSTEM [patent_app_type] => utility [patent_app_number] => 16/606554 [patent_app_country] => US [patent_app_date] => 2018-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4794 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 590 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16606554 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/606554
Circuit and charging method for an electrical energy storage system Apr 10, 2018 Issued
Array ( [id] => 16764493 [patent_doc_number] => 20210110075 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-15 [patent_title] => SYSTEM FOR AUTOMATED GENERATIVE DESIGN SYNTHESIS USING DATA FROM DESIGN TOOLS AND KNOWLEDGE FROM A DIGITAL TWIN [patent_app_type] => utility [patent_app_number] => 16/496678 [patent_app_country] => US [patent_app_date] => 2018-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6968 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16496678 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/496678
System for automated generative design synthesis using data from design tools and knowledge from a digital twin Mar 26, 2018 Issued
Array ( [id] => 14379901 [patent_doc_number] => 20190163863 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-30 [patent_title] => METHOD AND SYSTEM OF FORMING SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 15/933771 [patent_app_country] => US [patent_app_date] => 2018-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6605 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15933771 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/933771
Method and system of forming semiconductor device Mar 22, 2018 Issued
Array ( [id] => 15609895 [patent_doc_number] => 10586011 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-03-10 [patent_title] => System and method for pin automation for topology editing [patent_app_type] => utility [patent_app_number] => 15/928627 [patent_app_country] => US [patent_app_date] => 2018-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 5537 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15928627 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/928627
System and method for pin automation for topology editing Mar 21, 2018 Issued
Array ( [id] => 12867994 [patent_doc_number] => 20180181173 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-28 [patent_title] => AUTOMATIC GENERATION OF POWER MANAGEMENT SEQUENCE IN A SOC OR NOC [patent_app_type] => utility [patent_app_number] => 15/903298 [patent_app_country] => US [patent_app_date] => 2018-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9419 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -2 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15903298 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/903298
AUTOMATIC GENERATION OF POWER MANAGEMENT SEQUENCE IN A SOC OR NOC Feb 22, 2018 Abandoned
Array ( [id] => 12867997 [patent_doc_number] => 20180181174 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-28 [patent_title] => AUTOMATIC GENERATION OF POWER MANAGEMENT SEQUENCE IN A SOC OR NOC [patent_app_type] => utility [patent_app_number] => 15/903702 [patent_app_country] => US [patent_app_date] => 2018-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9407 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15903702 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/903702
Automatic generation of power management sequence in a SoC or NoC Feb 22, 2018 Issued
Array ( [id] => 14123777 [patent_doc_number] => 10248749 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-02 [patent_title] => Automated attribute propagation and hierarchical consistency checking for non-standard extensions [patent_app_type] => utility [patent_app_number] => 15/897655 [patent_app_country] => US [patent_app_date] => 2018-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4324 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15897655 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/897655
Automated attribute propagation and hierarchical consistency checking for non-standard extensions Feb 14, 2018 Issued
Array ( [id] => 12713824 [patent_doc_number] => 20180129774 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-10 [patent_title] => EARLY OVERLAY PREDICTION AND OVERLAY-AWARE MASK DESIGN [patent_app_type] => utility [patent_app_number] => 15/862782 [patent_app_country] => US [patent_app_date] => 2018-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6567 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15862782 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/862782
Early overlay prediction and overlay-aware mask design Jan 4, 2018 Issued
Array ( [id] => 13069501 [patent_doc_number] => 10055530 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-08-21 [patent_title] => Arrangement and method for facilitating electronics design in connection with 3D structures [patent_app_type] => utility [patent_app_number] => 15/840647 [patent_app_country] => US [patent_app_date] => 2017-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 16030 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15840647 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/840647
Arrangement and method for facilitating electronics design in connection with 3D structures Dec 12, 2017 Issued
Array ( [id] => 12629400 [patent_doc_number] => 20180101630 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-12 [patent_title] => PROCESS-METROLOGY REPRODUCIBILITY BANDS FOR LITHOGRAPHIC PHOTOMASKS [patent_app_type] => utility [patent_app_number] => 15/838423 [patent_app_country] => US [patent_app_date] => 2017-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6643 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15838423 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/838423
Process-metrology reproducibility bands for lithographic photomasks Dec 11, 2017 Issued
Array ( [id] => 12612783 [patent_doc_number] => 20180096091 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-05 [patent_title] => ADJUSTING SCAN CONNECTIONS BASED ON SCAN CONTROL LOCATIONS [patent_app_type] => utility [patent_app_number] => 15/831483 [patent_app_country] => US [patent_app_date] => 2017-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3617 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15831483 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/831483
Adjusting scan connections based on scan control locations Dec 4, 2017 Issued
Array ( [id] => 12242307 [patent_doc_number] => 20180075171 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-15 [patent_title] => 'AUTOMATED ATTRIBUTE PROPAGATION AND HIERARCHICAL CONSISTENCY CHECKING FOR NON-STANDARD EXTENSIONS' [patent_app_type] => utility [patent_app_number] => 15/814447 [patent_app_country] => US [patent_app_date] => 2017-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4416 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15814447 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/814447
Automated attribute propagation and hierarchical consistency checking for non-standard extensions Nov 15, 2017 Issued
Array ( [id] => 16263575 [patent_doc_number] => 10755011 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-25 [patent_title] => Detecting out-of-bounds violations in a hardware design using formal verification [patent_app_type] => utility [patent_app_number] => 15/784353 [patent_app_country] => US [patent_app_date] => 2017-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 13667 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15784353 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/784353
Detecting out-of-bounds violations in a hardware design using formal verification Oct 15, 2017 Issued
Array ( [id] => 12776272 [patent_doc_number] => 20180150592 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-31 [patent_title] => CELL STRUCTURES AND SEMICONDUCTOR DEVICES HAVING SAME [patent_app_type] => utility [patent_app_number] => 15/782232 [patent_app_country] => US [patent_app_date] => 2017-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16110 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15782232 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/782232
Cell structures and semiconductor devices having same Oct 11, 2017 Issued
Array ( [id] => 14189355 [patent_doc_number] => 20190114383 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-18 [patent_title] => CUSTOMIZING CIRCUIT LAYOUT DESIGN RULES FOR FABRICATION FACILITIES [patent_app_type] => utility [patent_app_number] => 15/782673 [patent_app_country] => US [patent_app_date] => 2017-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4328 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15782673 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/782673
Customizing circuit layout design rules for fabrication facilities Oct 11, 2017 Issued
Array ( [id] => 14188263 [patent_doc_number] => 20190113837 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-18 [patent_title] => METHODOLOGY FOR POST-INTEGRATION AWARENESS IN OPTICAL PROXIMITY CORRECTION [patent_app_type] => utility [patent_app_number] => 15/730830 [patent_app_country] => US [patent_app_date] => 2017-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4115 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15730830 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/730830
Methodology for post-integration awareness in optical proximity correction Oct 11, 2017 Issued
Array ( [id] => 14490091 [patent_doc_number] => 10331836 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-06-25 [patent_title] => Loop optimization for implementing circuit designs in hardware [patent_app_type] => utility [patent_app_number] => 15/730431 [patent_app_country] => US [patent_app_date] => 2017-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 12280 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15730431 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/730431
Loop optimization for implementing circuit designs in hardware Oct 10, 2017 Issued
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