Eric D. Lee

Array ( [id] => 19398802 [patent_doc_number] => 12073170 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-27 [patent_title] => Integrated circuit, system for and method of forming an integrated circuit [patent_app_type] => utility [patent_app_number] => 18/354423 [patent_app_country] => US [patent_app_date] => 2023-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 28 [patent_no_of_words] => 25744 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 333 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18354423 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18941339 [patent_doc_number] => 20240036478 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-01 [patent_title] => LITHOGRAPHY MODEL SIMULATION METHOD, PHOTOMASK GENERATING METHOD USING THE SAME, AND SEMICONDUCTOR DEVICE FABRICATION METHOD USING THE SAME [patent_app_type] => utility [patent_app_number] => 18/350611 [patent_app_country] => US [patent_app_date] => 2023-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7636 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18350611 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19642248 [patent_doc_number] => 20240416768 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-19 [patent_title] => POWER TRANSFER USING MULTI-WINDING ELECTRIC MACHINES [patent_app_type] => utility [patent_app_number] => 18/334634 [patent_app_country] => US [patent_app_date] => 2023-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7393 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18334634 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19574075 [patent_doc_number] => 20240378367 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-14 [patent_title] => STATIC VOLTAGE DROP PREDICTION SYSTEM AND METHOD [patent_app_type] => utility [patent_app_number] => 18/325678 [patent_app_country] => US [patent_app_date] => 2023-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10473 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18325678 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19443353 [patent_doc_number] => 12093621 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-17 [patent_title] => Detecting out-of-bounds violations in a hardware design using formal verification [patent_app_type] => utility [patent_app_number] => 18/202929 [patent_app_country] => US [patent_app_date] => 2023-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 13779 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18202929 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19669738 [patent_doc_number] => 12182490 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-31 [patent_title] => Semiconductor design automation system and computing system including the same [patent_app_type] => utility [patent_app_number] => 18/316405 [patent_app_country] => US [patent_app_date] => 2023-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6238 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18316405 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19596021 [patent_doc_number] => 12153869 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-11-26 [patent_title] => Optimized layout cell [patent_app_type] => utility [patent_app_number] => 18/313844 [patent_app_country] => US [patent_app_date] => 2023-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 7857 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18313844 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18773107 [patent_doc_number] => 20230367936 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-16 [patent_title] => VERIFICATION METHOD, ELECTRONIC DEVICE AND STORAGE MEDIUM [patent_app_type] => utility [patent_app_number] => 18/313654 [patent_app_country] => US [patent_app_date] => 2023-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4935 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18313654 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19558840 [patent_doc_number] => 20240370632 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-07 [patent_title] => METHOD FOR PERFORMING DESIGN RULE CHECKS [patent_app_type] => utility [patent_app_number] => 18/312514 [patent_app_country] => US [patent_app_date] => 2023-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4640 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18312514 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19545357 [patent_doc_number] => 20240362393 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-31 [patent_title] => PREDICTION OF ROUTING CONGESTION [patent_app_type] => utility [patent_app_number] => 18/139659 [patent_app_country] => US [patent_app_date] => 2023-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5471 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18139659 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18554206 [patent_doc_number] => 20230252219 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-10 [patent_title] => METHOD AND SYSTEM OF FORMING SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/302813 [patent_app_country] => US [patent_app_date] => 2023-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6713 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18302813 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18728245 [patent_doc_number] => 20230342538 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-26 [patent_title] => MODEL-DRIVEN APPROACH FOR FAILURE MODE, EFFECTS, AND DIAGNOSTIC ANALYSIS (FMEDA) AUTOMATION FOR HARDWARE INTELLECTUAL PROPERTY OF COMPLEX ELECTRONIC SYSTEMS [patent_app_type] => utility [patent_app_number] => 18/301248 [patent_app_country] => US [patent_app_date] => 2023-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5291 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18301248 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19276315 [patent_doc_number] => 12026445 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-07-02 [patent_title] => Method and apparatus for photonic circuit simulation [patent_app_type] => utility [patent_app_number] => 18/295355 [patent_app_country] => US [patent_app_date] => 2023-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 9348 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18295355 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19015168 [patent_doc_number] => 11922101 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-05 [patent_title] => Integrated circuits as a service [patent_app_type] => utility [patent_app_number] => 18/123422 [patent_app_country] => US [patent_app_date] => 2023-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 19179 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18123422 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18998086 [patent_doc_number] => 11914933 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-27 [patent_title] => Generation of dynamic design flows for integrated circuits [patent_app_type] => utility [patent_app_number] => 18/182637 [patent_app_country] => US [patent_app_date] => 2023-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 26990 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18182637 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20027465 [patent_doc_number] => 20250165687 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-22 [patent_title] => DESIGN METHOD FOR FLIP-FLOP UNIT [patent_app_type] => utility [patent_app_number] => 18/832270 [patent_app_country] => US [patent_app_date] => 2023-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7844 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18832270 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18599270 [patent_doc_number] => 20230274070 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-31 [patent_title] => GENERATING ROUTES FOR AN INTEGRATED CIRCUIT DESIGN WITH NON-PREFERRED DIRECTION CURVILINEAR WIRING [patent_app_type] => utility [patent_app_number] => 18/110335 [patent_app_country] => US [patent_app_date] => 2023-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22354 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18110335 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20507357 [patent_doc_number] => 12541634 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-03 [patent_title] => Routing non-preferred direction wiring layers of an integrated circuit by minimizing vias between these layers [patent_app_type] => utility [patent_app_number] => 18/110343 [patent_app_country] => US [patent_app_date] => 2023-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 31 [patent_no_of_words] => 17520 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18110343 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18532160 [patent_doc_number] => 20230237232 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-27 [patent_title] => WORK SUPPORT DEVICE, WORK SUPPORT SYSTEM, AND ANALYSIS PROGRAM [patent_app_type] => utility [patent_app_number] => 18/099213 [patent_app_country] => US [patent_app_date] => 2023-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6790 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18099213 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19313435 [patent_doc_number] => 12039250 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-16 [patent_title] => Integrated circuit device design method and system [patent_app_type] => utility [patent_app_number] => 18/156671 [patent_app_country] => US [patent_app_date] => 2023-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7905 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18156671 [rel_patent_id] =>[rel_patent_doc_number] =>)