Eric D. Lee

Array ( [id] => 19596021 [patent_doc_number] => 12153869 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-11-26 [patent_title] => Optimized layout cell [patent_app_type] => utility [patent_app_number] => 18/313844 [patent_app_country] => US [patent_app_date] => 2023-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 7857 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18313844 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18554206 [patent_doc_number] => 20230252219 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-10 [patent_title] => METHOD AND SYSTEM OF FORMING SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/302813 [patent_app_country] => US [patent_app_date] => 2023-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6713 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18302813 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19276315 [patent_doc_number] => 12026445 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-07-02 [patent_title] => Method and apparatus for photonic circuit simulation [patent_app_type] => utility [patent_app_number] => 18/295355 [patent_app_country] => US [patent_app_date] => 2023-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 9348 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18295355 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19015168 [patent_doc_number] => 11922101 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-05 [patent_title] => Integrated circuits as a service [patent_app_type] => utility [patent_app_number] => 18/123422 [patent_app_country] => US [patent_app_date] => 2023-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 19179 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18123422 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18998086 [patent_doc_number] => 11914933 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-27 [patent_title] => Generation of dynamic design flows for integrated circuits [patent_app_type] => utility [patent_app_number] => 18/182637 [patent_app_country] => US [patent_app_date] => 2023-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 26990 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18182637 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18614637 [patent_doc_number] => 20230281374 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-07 [patent_title] => ROUTING NON-PREFERRED DIRECTION WIRING LAYERS OF AN INTEGRATED CIRCUIT BY MINIMIZING VIAS BETWEEN THESE LAYERS [patent_app_type] => utility [patent_app_number] => 18/110343 [patent_app_country] => US [patent_app_date] => 2023-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22345 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18110343 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18599270 [patent_doc_number] => 20230274070 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-31 [patent_title] => GENERATING ROUTES FOR AN INTEGRATED CIRCUIT DESIGN WITH NON-PREFERRED DIRECTION CURVILINEAR WIRING [patent_app_type] => utility [patent_app_number] => 18/110335 [patent_app_country] => US [patent_app_date] => 2023-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22354 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18110335 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19313435 [patent_doc_number] => 12039250 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-16 [patent_title] => Integrated circuit device design method and system [patent_app_type] => utility [patent_app_number] => 18/156671 [patent_app_country] => US [patent_app_date] => 2023-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7905 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18156671 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19443365 [patent_doc_number] => 12093634 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-17 [patent_title] => Path delay prediction method for integrated circuit based on feature selection and deep learning [patent_app_type] => utility [patent_app_number] => 18/567044 [patent_app_country] => US [patent_app_date] => 2023-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 6834 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 346 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18567044 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18337508 [patent_doc_number] => 20230129457 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-27 [patent_title] => MASK RULE CHECKING FOR CURVILINEAR MASKS FOR ELECTRONIC CIRCUITS [patent_app_type] => utility [patent_app_number] => 18/088195 [patent_app_country] => US [patent_app_date] => 2022-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12387 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18088195 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19174845 [patent_doc_number] => 20240160819 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-16 [patent_title] => FAILURE DIAGNOSIS ASSISTING DEVICE [patent_app_type] => utility [patent_app_number] => 18/080785 [patent_app_country] => US [patent_app_date] => 2022-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5969 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18080785 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19303923 [patent_doc_number] => 20240232503 [patent_country] => US [patent_kind] => A9 [patent_issue_date] => 2024-07-11 [patent_title] => REINFORCEMENT LEARNING BASED CORRECTION OF TIMING FAILURES [patent_app_type] => utility [patent_app_number] => 18/063408 [patent_app_country] => US [patent_app_date] => 2022-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9375 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18063408 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19303923 [patent_doc_number] => 20240232503 [patent_country] => US [patent_kind] => A9 [patent_issue_date] => 2024-07-11 [patent_title] => REINFORCEMENT LEARNING BASED CORRECTION OF TIMING FAILURES [patent_app_type] => utility [patent_app_number] => 18/063408 [patent_app_country] => US [patent_app_date] => 2022-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9375 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18063408 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18438712 [patent_doc_number] => 20230186007 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-15 [patent_title] => SYSTEM AND METHOD FOR OPTIMIZING INTEGRATED CIRCUIT LAYOUT BASED ON NEURAL NETWORK [patent_app_type] => utility [patent_app_number] => 18/062922 [patent_app_country] => US [patent_app_date] => 2022-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10080 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 323 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18062922 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19220267 [patent_doc_number] => 20240184971 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-06 [patent_title] => BIT LINE ALIGNMENT FOR THE REDUCTION OF SOFT ERRORS [patent_app_type] => utility [patent_app_number] => 18/062098 [patent_app_country] => US [patent_app_date] => 2022-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7034 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18062098 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20215348 [patent_doc_number] => 12412002 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-09 [patent_title] => Systems and methods for adding a design element to a design [patent_app_type] => utility [patent_app_number] => 17/994376 [patent_app_country] => US [patent_app_date] => 2022-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 7351 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17994376 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20215348 [patent_doc_number] => 12412002 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-09 [patent_title] => Systems and methods for adding a design element to a design [patent_app_type] => utility [patent_app_number] => 17/994376 [patent_app_country] => US [patent_app_date] => 2022-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 7351 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17994376 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18454700 [patent_doc_number] => 20230195980 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-22 [patent_title] => Integrated Circuit Generation Using an Integrated Circuit Shell [patent_app_type] => utility [patent_app_number] => 17/992976 [patent_app_country] => US [patent_app_date] => 2022-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11086 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17992976 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18407893 [patent_doc_number] => 20230169246 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-01 [patent_title] => INTERACTIVE COMPACTION TOOL FOR ELECTRONIC DESIGN AUTOMATION [patent_app_type] => utility [patent_app_number] => 17/992876 [patent_app_country] => US [patent_app_date] => 2022-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 23500 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17992876 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18513601 [patent_doc_number] => 20230229836 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-20 [patent_title] => GENERATING AND DISPLAY AN ANIMATION OF A PREDICTED OVERLAP SHAPE IN AN IC DESIGN [patent_app_type] => utility [patent_app_number] => 17/992907 [patent_app_country] => US [patent_app_date] => 2022-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12476 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17992907 [rel_patent_id] =>[rel_patent_doc_number] =>)