Search

Eric D. Lee

Examiner (ID: 17546)

Most Active Art Unit
2851
Art Unit(s)
2851, 2825
Total Applications
769
Issued Applications
617
Pending Applications
44
Abandoned Applications
124

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 15984743 [patent_doc_number] => 10672709 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-02 [patent_title] => Power grid, IC and method for placing power grid [patent_app_type] => utility [patent_app_number] => 15/651165 [patent_app_country] => US [patent_app_date] => 2017-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7435 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15651165 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/651165
Power grid, IC and method for placing power grid Jul 16, 2017 Issued
Array ( [id] => 13830871 [patent_doc_number] => 20190018920 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-17 [patent_title] => SYSTEM AND METHOD FOR SIMULATING RELIABILITY OF CIRCUIT DESIGN [patent_app_type] => utility [patent_app_number] => 15/650131 [patent_app_country] => US [patent_app_date] => 2017-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3800 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15650131 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/650131
System and method for simulating reliability of circuit design Jul 13, 2017 Issued
Array ( [id] => 15059513 [patent_doc_number] => 10460063 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-10-29 [patent_title] => Integrated circuit routing based on enhanced topology [patent_app_type] => utility [patent_app_number] => 15/649402 [patent_app_country] => US [patent_app_date] => 2017-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 8027 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15649402 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/649402
Integrated circuit routing based on enhanced topology Jul 12, 2017 Issued
Array ( [id] => 14767197 [patent_doc_number] => 10394995 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-08-27 [patent_title] => Methods and systems for schematic driven 2D chaining in an integrated circuit layout [patent_app_type] => utility [patent_app_number] => 15/649209 [patent_app_country] => US [patent_app_date] => 2017-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6077 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 288 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15649209 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/649209
Methods and systems for schematic driven 2D chaining in an integrated circuit layout Jul 12, 2017 Issued
Array ( [id] => 15059515 [patent_doc_number] => 10460064 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-10-29 [patent_title] => Partition-aware grid graph based hierarchical global routing [patent_app_type] => utility [patent_app_number] => 15/649415 [patent_app_country] => US [patent_app_date] => 2017-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 23 [patent_no_of_words] => 9908 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15649415 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/649415
Partition-aware grid graph based hierarchical global routing Jul 12, 2017 Issued
Array ( [id] => 15059519 [patent_doc_number] => 10460066 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-10-29 [patent_title] => Routing framework to resolve single-entry constraint violations for integrated circuit designs [patent_app_type] => utility [patent_app_number] => 15/649443 [patent_app_country] => US [patent_app_date] => 2017-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7787 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15649443 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/649443
Routing framework to resolve single-entry constraint violations for integrated circuit designs Jul 12, 2017 Issued
Array ( [id] => 15059517 [patent_doc_number] => 10460065 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-10-29 [patent_title] => Routing topology generation using spine-like tree structure [patent_app_type] => utility [patent_app_number] => 15/649426 [patent_app_country] => US [patent_app_date] => 2017-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8587 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15649426 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/649426
Routing topology generation using spine-like tree structure Jul 12, 2017 Issued
Array ( [id] => 12689263 [patent_doc_number] => 20180121587 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-03 [patent_title] => SIMULATION METHODS AND SYSTEMS FOR PREDICTING SER [patent_app_type] => utility [patent_app_number] => 15/645227 [patent_app_country] => US [patent_app_date] => 2017-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7033 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15645227 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/645227
Simulation methods and systems for predicting SER Jul 9, 2017 Issued
Array ( [id] => 12612768 [patent_doc_number] => 20180096086 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-05 [patent_title] => DYNAMIC FREQUENCY BOOSTING EXPLOITING PATH DELAY VARIABILITY IN INTEGRATED CIRCUITS [patent_app_type] => utility [patent_app_number] => 15/644760 [patent_app_country] => US [patent_app_date] => 2017-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9671 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15644760 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/644760
Dynamic frequency boosting exploiting path delay variability in integrated circuits Jul 7, 2017 Issued
Array ( [id] => 16065819 [patent_doc_number] => 10691862 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-23 [patent_title] => Layouts for connecting contacts with metal tabs or vias [patent_app_type] => utility [patent_app_number] => 15/644288 [patent_app_country] => US [patent_app_date] => 2017-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4791 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15644288 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/644288
Layouts for connecting contacts with metal tabs or vias Jul 6, 2017 Issued
Array ( [id] => 14490089 [patent_doc_number] => 10331835 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-25 [patent_title] => ASIC design methodology for converting RTL HDL to a light netlist [patent_app_type] => utility [patent_app_number] => 15/644696 [patent_app_country] => US [patent_app_date] => 2017-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5437 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15644696 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/644696
ASIC design methodology for converting RTL HDL to a light netlist Jul 6, 2017 Issued
Array ( [id] => 16479545 [patent_doc_number] => 10854499 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-01 [patent_title] => Integrated circuit, system for and method of forming an integrated circuit [patent_app_type] => utility [patent_app_number] => 15/643825 [patent_app_country] => US [patent_app_date] => 2017-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 28 [patent_no_of_words] => 25175 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15643825 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/643825
Integrated circuit, system for and method of forming an integrated circuit Jul 6, 2017 Issued
Array ( [id] => 12161392 [patent_doc_number] => 20180032658 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-01 [patent_title] => 'SYSTEM AND METHOD OF DESIGNING INTEGRATED CIRCUIT BY CONSIDERING LOCAL LAYOUT EFFECT' [patent_app_type] => utility [patent_app_number] => 15/643472 [patent_app_country] => US [patent_app_date] => 2017-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 13353 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15643472 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/643472
System and method of designing integrated circuit by considering local layout effect Jul 6, 2017 Issued
Array ( [id] => 15313673 [patent_doc_number] => 10521543 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-12-31 [patent_title] => Systems and methods for estimating the future electrical resistance of a wire of a partially routed net [patent_app_type] => utility [patent_app_number] => 15/642848 [patent_app_country] => US [patent_app_date] => 2017-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6722 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 282 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15642848 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/642848
Systems and methods for estimating the future electrical resistance of a wire of a partially routed net Jul 5, 2017 Issued
Array ( [id] => 15578761 [patent_doc_number] => 10579767 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-03-03 [patent_title] => Systems and methods for routing a clock net with multiple layer ranges [patent_app_type] => utility [patent_app_number] => 15/640999 [patent_app_country] => US [patent_app_date] => 2017-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8610 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15640999 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/640999
Systems and methods for routing a clock net with multiple layer ranges Jul 2, 2017 Issued
Array ( [id] => 16018565 [patent_doc_number] => 20200184126 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-11 [patent_title] => DESIGN SUPPORT METHOD, DESIGN SUPPORT APPARATUS, AND A NON-TRANSITORY RECORDING MEDIUM STORING A DESIGN SUPPORT PROGRAM [patent_app_type] => utility [patent_app_number] => 16/614552 [patent_app_country] => US [patent_app_date] => 2017-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8688 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16614552 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/614552
Support method, design support apparatus, and a non-transitory recording medium storing a design support program Jun 7, 2017 Issued
Array ( [id] => 18684625 [patent_doc_number] => 11780338 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-10 [patent_title] => Time delay toll system for charging piles and its method [patent_app_type] => utility [patent_app_number] => 15/607635 [patent_app_country] => US [patent_app_date] => 2017-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2101 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 322 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15607635 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/607635
Time delay toll system for charging piles and its method May 28, 2017 Issued
Array ( [id] => 11824761 [patent_doc_number] => 20170213698 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-27 [patent_title] => 'Method and System for Forming Patterns Using Charged Particle Beam Lithography with Variable Pattern Dosage' [patent_app_type] => utility [patent_app_number] => 15/481677 [patent_app_country] => US [patent_app_date] => 2017-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 11535 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15481677 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/481677
Method and System for Forming Patterns Using Charged Particle Beam Lithography with Variable Pattern Dosage Apr 6, 2017 Abandoned
Array ( [id] => 18155132 [patent_doc_number] => 11568112 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-31 [patent_title] => System design support apparatus and system design support method [patent_app_type] => utility [patent_app_number] => 16/345726 [patent_app_country] => US [patent_app_date] => 2017-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 5308 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16345726 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/345726
System design support apparatus and system design support method Mar 29, 2017 Issued
Array ( [id] => 12187798 [patent_doc_number] => 20180046734 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-15 [patent_title] => 'AUTOMATED ATTRIBUTE PROPAGATION AND HIERARCHICAL CONSISTENCY CHECKING FOR NON-STANDARD EXTENSIONS' [patent_app_type] => utility [patent_app_number] => 15/430864 [patent_app_country] => US [patent_app_date] => 2017-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4385 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15430864 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/430864
Automated attribute propagation and hierarchical consistency checking for non-standard extensions Feb 12, 2017 Issued
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