Eric D. Lee

Array ( [id] => 18684625 [patent_doc_number] => 11780338 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-10 [patent_title] => Time delay toll system for charging piles and its method [patent_app_type] => utility [patent_app_number] => 15/607635 [patent_app_country] => US [patent_app_date] => 2017-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2101 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 322 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15607635 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11824761 [patent_doc_number] => 20170213698 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-27 [patent_title] => 'Method and System for Forming Patterns Using Charged Particle Beam Lithography with Variable Pattern Dosage' [patent_app_type] => utility [patent_app_number] => 15/481677 [patent_app_country] => US [patent_app_date] => 2017-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 11535 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15481677 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18155132 [patent_doc_number] => 11568112 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-31 [patent_title] => System design support apparatus and system design support method [patent_app_type] => utility [patent_app_number] => 16/345726 [patent_app_country] => US [patent_app_date] => 2017-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 5308 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16345726 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12187798 [patent_doc_number] => 20180046734 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-15 [patent_title] => 'AUTOMATED ATTRIBUTE PROPAGATION AND HIERARCHICAL CONSISTENCY CHECKING FOR NON-STANDARD EXTENSIONS' [patent_app_type] => utility [patent_app_number] => 15/430864 [patent_app_country] => US [patent_app_date] => 2017-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4385 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15430864 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11591950 [patent_doc_number] => 20170116361 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-04-27 [patent_title] => 'CHARACTERIZING CELL USING INPUT WAVEFORMS WITH DIFFERENT TAIL CHARACTERISTICS' [patent_app_type] => utility [patent_app_number] => 15/400519 [patent_app_country] => US [patent_app_date] => 2017-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 11837 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15400519 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16329941 [patent_doc_number] => 20200300907 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-24 [patent_title] => ANALOG-CIRCUIT FAULT DIAGNOSIS METHOD BASED ON CONTINUOUS WAVELET ANALYSIS AND ELM NETWORK [patent_app_type] => utility [patent_app_number] => 16/088079 [patent_app_country] => US [patent_app_date] => 2017-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3363 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16088079 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11709266 [patent_doc_number] => 20170177765 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-22 [patent_title] => 'TEST CASE GENERATION' [patent_app_type] => utility [patent_app_number] => 15/382984 [patent_app_country] => US [patent_app_date] => 2016-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5140 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15382984 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15373937 [patent_doc_number] => 10528689 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-01-07 [patent_title] => Verification process for IJTAG based test pattern migration [patent_app_type] => utility [patent_app_number] => 15/364049 [patent_app_country] => US [patent_app_date] => 2016-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4526 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15364049 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12776260 [patent_doc_number] => 20180150588 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-31 [patent_title] => INTERCONNECT REUSE RESOLUTION WITH BUMP COMPENSATION IN A PACKAGE DESIGN [patent_app_type] => utility [patent_app_number] => 15/362346 [patent_app_country] => US [patent_app_date] => 2016-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7436 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15362346 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14669919 [patent_doc_number] => 10372861 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-06 [patent_title] => Method of macro placement and a non-transitory computer readable medium thereof [patent_app_type] => utility [patent_app_number] => 15/362700 [patent_app_country] => US [patent_app_date] => 2016-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 19 [patent_no_of_words] => 2500 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15362700 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11672681 [patent_doc_number] => 20170161403 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-08 [patent_title] => 'ASSERTION STATEMENT CHECK AND DEBUG' [patent_app_type] => utility [patent_app_number] => 15/362510 [patent_app_country] => US [patent_app_date] => 2016-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6704 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15362510 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17106548 [patent_doc_number] => 11126766 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-21 [patent_title] => System and method for element quality improvement in 3D quadrilateral-dominant surface meshes [patent_app_type] => utility [patent_app_number] => 16/336641 [patent_app_country] => US [patent_app_date] => 2016-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 21 [patent_no_of_words] => 11708 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 252 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16336641 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15285023 [patent_doc_number] => 10515176 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-12-24 [patent_title] => System and method for visualizing component data routes [patent_app_type] => utility [patent_app_number] => 15/298178 [patent_app_country] => US [patent_app_date] => 2016-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 34 [patent_no_of_words] => 7703 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15298178 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12647829 [patent_doc_number] => 20180107774 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-19 [patent_title] => TIMING ANALYSIS FOR ELECTRONIC DESIGN AUTOMATION OF PARALLEL MULTI-STATE DRIVER CIRCUITS [patent_app_type] => utility [patent_app_number] => 15/297979 [patent_app_country] => US [patent_app_date] => 2016-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7332 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15297979 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11438288 [patent_doc_number] => 20170039309 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-02-09 [patent_title] => 'Transient IR-drop waveform measurement system and method for high speed integrated circuit' [patent_app_type] => utility [patent_app_number] => 15/297080 [patent_app_country] => US [patent_app_date] => 2016-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9215 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15297080 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14331351 [patent_doc_number] => 10296696 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-21 [patent_title] => Semiconductor design assisting device and semiconductor design assisting method [patent_app_type] => utility [patent_app_number] => 15/296092 [patent_app_country] => US [patent_app_date] => 2016-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 37 [patent_no_of_words] => 13629 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 516 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15296092 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12647838 [patent_doc_number] => 20180107777 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-19 [patent_title] => OPTIMIZING AN INTEGRATED CIRCUIT (IC) DESIGN COMPRISING AT LEAST ONE WIDE-GATE OR WIDE-BUS [patent_app_type] => utility [patent_app_number] => 15/295837 [patent_app_country] => US [patent_app_date] => 2016-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8984 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15295837 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11367506 [patent_doc_number] => 20170005487 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-01-05 [patent_title] => 'METHOD OF FORMING A BALANCING CIRCUIT FOR A PLURALITY OF BATTERY CELLS AND STRUCTURE THEREFOR' [patent_app_type] => utility [patent_app_number] => 15/269587 [patent_app_country] => US [patent_app_date] => 2016-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8151 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 14 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15269587 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11509456 [patent_doc_number] => 09600616 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-03-21 [patent_title] => 'Assuring chip reliability with automatic generation of drivers and assertions' [patent_app_type] => utility [patent_app_number] => 15/264336 [patent_app_country] => US [patent_app_date] => 2016-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5229 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15264336 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17196500 [patent_doc_number] => 11165271 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-02 [patent_title] => Control device and method for charging a non-aqueous rechargeable metal-air battery [patent_app_type] => utility [patent_app_number] => 16/312218 [patent_app_country] => US [patent_app_date] => 2016-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 6790 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16312218 [rel_patent_id] =>[rel_patent_doc_number] =>)