Search

Eric D. Lee

Examiner (ID: 17546)

Most Active Art Unit
2851
Art Unit(s)
2851, 2825
Total Applications
769
Issued Applications
617
Pending Applications
44
Abandoned Applications
124

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11948982 [patent_doc_number] => 20170253133 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-07 [patent_title] => 'SOLAR POWERED VEHICLE INTEGRATED BATTERY CHARGER' [patent_app_type] => utility [patent_app_number] => 15/062523 [patent_app_country] => US [patent_app_date] => 2016-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4732 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15062523 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/062523
SOLAR POWERED VEHICLE INTEGRATED BATTERY CHARGER Mar 6, 2016 Abandoned
Array ( [id] => 11316018 [patent_doc_number] => 20160352128 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-01 [patent_title] => 'REGULATOR WITH HIGH SPEED NONLINEAR COMPENSATION' [patent_app_type] => utility [patent_app_number] => 15/062348 [patent_app_country] => US [patent_app_date] => 2016-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 9223 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15062348 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/062348
Regulator with high speed nonlinear compensation Mar 6, 2016 Issued
Array ( [id] => 11104251 [patent_doc_number] => 20160301221 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-13 [patent_title] => 'SYSTEMS AND METHODS FOR IMPROVING CELL BALANCING AND CELL FAILURE DETECTION' [patent_app_type] => utility [patent_app_number] => 15/061290 [patent_app_country] => US [patent_app_date] => 2016-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7155 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15061290 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/061290
Systems and methods for improving cell balancing and cell failure detection Mar 3, 2016 Issued
Array ( [id] => 11518043 [patent_doc_number] => 20170085117 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-23 [patent_title] => 'BATTERY-SHAPED WIRELESS DEVICE' [patent_app_type] => utility [patent_app_number] => 15/061988 [patent_app_country] => US [patent_app_date] => 2016-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 9904 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15061988 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/061988
BATTERY-SHAPED WIRELESS DEVICE Mar 3, 2016 Abandoned
Array ( [id] => 11823228 [patent_doc_number] => 20170212165 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-27 [patent_title] => 'RESISTANCE MEASUREMENT-DEPENDENT INTEGRATED CIRCUIT CHIP RELIABILITY ESTIMATION' [patent_app_type] => utility [patent_app_number] => 15/005819 [patent_app_country] => US [patent_app_date] => 2016-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6530 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15005819 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/005819
RESISTANCE MEASUREMENT-DEPENDENT INTEGRATED CIRCUIT CHIP RELIABILITY ESTIMATION Jan 24, 2016 Abandoned
Array ( [id] => 11824040 [patent_doc_number] => 20170212977 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-27 [patent_title] => 'AREA AND/OR POWER OPTIMIZATION THROUGH POST-LAYOUT MODIFICATION OF INTEGRATED CIRCUIT (IC) DESIGN BLOCKS' [patent_app_type] => utility [patent_app_number] => 15/002550 [patent_app_country] => US [patent_app_date] => 2016-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9650 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15002550 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/002550
Area and/or power optimization through post-layout modification of integrated circuit (IC) design blocks Jan 20, 2016 Issued
Array ( [id] => 11817107 [patent_doc_number] => 09721059 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-08-01 [patent_title] => 'Post-layout thermal-aware integrated circuit performance modeling' [patent_app_type] => utility [patent_app_number] => 15/002808 [patent_app_country] => US [patent_app_date] => 2016-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 9712 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 254 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15002808 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/002808
Post-layout thermal-aware integrated circuit performance modeling Jan 20, 2016 Issued
Array ( [id] => 12088449 [patent_doc_number] => 09842179 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-12-12 [patent_title] => 'Recording medium, ranking method, and information processing device' [patent_app_type] => utility [patent_app_number] => 15/001310 [patent_app_country] => US [patent_app_date] => 2016-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 35 [patent_no_of_words] => 8975 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 239 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15001310 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/001310
Recording medium, ranking method, and information processing device Jan 19, 2016 Issued
Array ( [id] => 12292011 [patent_doc_number] => 09934348 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-04-03 [patent_title] => Adjusting scan connections based on scan control locations [patent_app_type] => utility [patent_app_number] => 14/973764 [patent_app_country] => US [patent_app_date] => 2015-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3617 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14973764 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/973764
Adjusting scan connections based on scan control locations Dec 17, 2015 Issued
Array ( [id] => 11752567 [patent_doc_number] => 09710582 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-07-18 [patent_title] => 'Delivering circuit designs for programmable integrated circuits' [patent_app_type] => utility [patent_app_number] => 14/974217 [patent_app_country] => US [patent_app_date] => 2015-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 8618 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14974217 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/974217
Delivering circuit designs for programmable integrated circuits Dec 17, 2015 Issued
Array ( [id] => 11709286 [patent_doc_number] => 20170177785 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-22 [patent_title] => 'Computer Implemented System and Method for Modifying a Layout of Standard Cells Defining a Circuit Component' [patent_app_type] => utility [patent_app_number] => 14/975482 [patent_app_country] => US [patent_app_date] => 2015-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 9153 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14975482 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/975482
Computer implemented system and method for modifying a layout of standard cells defining a circuit component Dec 17, 2015 Issued
Array ( [id] => 12292026 [patent_doc_number] => 09934353 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-04-03 [patent_title] => Focus measurements using scatterometry metrology [patent_app_type] => utility [patent_app_number] => 14/974732 [patent_app_country] => US [patent_app_date] => 2015-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 4093 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14974732 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/974732
Focus measurements using scatterometry metrology Dec 17, 2015 Issued
Array ( [id] => 11917549 [patent_doc_number] => 09785738 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-10-10 [patent_title] => 'System and method for evaluating spanning trees' [patent_app_type] => utility [patent_app_number] => 14/972809 [patent_app_country] => US [patent_app_date] => 2015-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 10186 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14972809 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/972809
System and method for evaluating spanning trees Dec 16, 2015 Issued
Array ( [id] => 14767207 [patent_doc_number] => 10395000 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-08-27 [patent_title] => Methods, systems, and computer program products for implementing an electronic design using voltage-based electrical analyses and simulations with corrections [patent_app_type] => utility [patent_app_number] => 14/973341 [patent_app_country] => US [patent_app_date] => 2015-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10661 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 385 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14973341 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/973341
Methods, systems, and computer program products for implementing an electronic design using voltage-based electrical analyses and simulations with corrections Dec 16, 2015 Issued
Array ( [id] => 12108342 [patent_doc_number] => 09864827 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-01-09 [patent_title] => 'System and method for modeling electronic circuit designs' [patent_app_type] => utility [patent_app_number] => 14/973064 [patent_app_country] => US [patent_app_date] => 2015-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8069 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14973064 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/973064
System and method for modeling electronic circuit designs Dec 16, 2015 Issued
Array ( [id] => 14642905 [patent_doc_number] => 10366197 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-30 [patent_title] => Coupling aware wire capacitance adjust at global routing [patent_app_type] => utility [patent_app_number] => 14/973631 [patent_app_country] => US [patent_app_date] => 2015-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 7677 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14973631 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/973631
Coupling aware wire capacitance adjust at global routing Dec 16, 2015 Issued
Array ( [id] => 14427723 [patent_doc_number] => 10318667 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-11 [patent_title] => Test case generation [patent_app_type] => utility [patent_app_number] => 14/971300 [patent_app_country] => US [patent_app_date] => 2015-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5002 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14971300 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/971300
Test case generation Dec 15, 2015 Issued
Array ( [id] => 14490103 [patent_doc_number] => 10331842 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-25 [patent_title] => Methods and apparatus for automated design of semiconductor photonic devices [patent_app_type] => utility [patent_app_number] => 14/972007 [patent_app_country] => US [patent_app_date] => 2015-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 34 [patent_no_of_words] => 17723 [patent_no_of_claims] => 73 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14972007 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/972007
Methods and apparatus for automated design of semiconductor photonic devices Dec 15, 2015 Issued
Array ( [id] => 12292005 [patent_doc_number] => 09934346 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-04-03 [patent_title] => Source mask optimization to reduce stochastic effects [patent_app_type] => utility [patent_app_number] => 14/968561 [patent_app_country] => US [patent_app_date] => 2015-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 16241 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14968561 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/968561
Source mask optimization to reduce stochastic effects Dec 13, 2015 Issued
Array ( [id] => 11258691 [patent_doc_number] => 09483591 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-11-01 [patent_title] => 'Assuring chip reliability with automatic generation of drivers and assertions' [patent_app_type] => utility [patent_app_number] => 14/953094 [patent_app_country] => US [patent_app_date] => 2015-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5198 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 27 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14953094 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/953094
Assuring chip reliability with automatic generation of drivers and assertions Nov 26, 2015 Issued
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