Search

Eric D. Lee

Examiner (ID: 1963, Phone: (571)270-7098 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2851, 2825
Total Applications
773
Issued Applications
618
Pending Applications
46
Abandoned Applications
125

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 14427723 [patent_doc_number] => 10318667 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-11 [patent_title] => Test case generation [patent_app_type] => utility [patent_app_number] => 14/971300 [patent_app_country] => US [patent_app_date] => 2015-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5002 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14971300 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/971300
Test case generation Dec 15, 2015 Issued
Array ( [id] => 14490103 [patent_doc_number] => 10331842 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-25 [patent_title] => Methods and apparatus for automated design of semiconductor photonic devices [patent_app_type] => utility [patent_app_number] => 14/972007 [patent_app_country] => US [patent_app_date] => 2015-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 34 [patent_no_of_words] => 17723 [patent_no_of_claims] => 73 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14972007 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/972007
Methods and apparatus for automated design of semiconductor photonic devices Dec 15, 2015 Issued
Array ( [id] => 12292005 [patent_doc_number] => 09934346 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-04-03 [patent_title] => Source mask optimization to reduce stochastic effects [patent_app_type] => utility [patent_app_number] => 14/968561 [patent_app_country] => US [patent_app_date] => 2015-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 16241 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14968561 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/968561
Source mask optimization to reduce stochastic effects Dec 13, 2015 Issued
Array ( [id] => 11258691 [patent_doc_number] => 09483591 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-11-01 [patent_title] => 'Assuring chip reliability with automatic generation of drivers and assertions' [patent_app_type] => utility [patent_app_number] => 14/953094 [patent_app_country] => US [patent_app_date] => 2015-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5198 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 27 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14953094 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/953094
Assuring chip reliability with automatic generation of drivers and assertions Nov 26, 2015 Issued
Array ( [id] => 11653361 [patent_doc_number] => 20170149266 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-25 [patent_title] => 'Inductive Charging Device for Charging Batteries' [patent_app_type] => utility [patent_app_number] => 14/952753 [patent_app_country] => US [patent_app_date] => 2015-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3220 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14952753 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/952753
Inductive charging device for charging batteries Nov 24, 2015 Issued
Array ( [id] => 11186783 [patent_doc_number] => 09418187 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-08-16 [patent_title] => 'Cycle-accurate replay and debugging of running FPGA systems' [patent_app_type] => utility [patent_app_number] => 14/940686 [patent_app_country] => US [patent_app_date] => 2015-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 8409 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14940686 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/940686
Cycle-accurate replay and debugging of running FPGA systems Nov 12, 2015 Issued
Array ( [id] => 11459148 [patent_doc_number] => 20170053054 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-02-23 [patent_title] => 'MITIGATING WIRE CAPACITANCE IN AN INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 14/830938 [patent_app_country] => US [patent_app_date] => 2015-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8338 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14830938 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/830938
Mitigating wire capacitance in an integrated circuit Aug 19, 2015 Issued
Array ( [id] => 10709124 [patent_doc_number] => 20160055271 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-25 [patent_title] => 'DATA STRUCTURE OF DESIGN DATA OF SEMICONDUCTOR INTEGRATED CIRCUIT AND APPARATUS AND METHOD OF DESIGNING SEMICONDUCTOR INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 14/830652 [patent_app_country] => US [patent_app_date] => 2015-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 9654 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14830652 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/830652
DATA STRUCTURE OF DESIGN DATA OF SEMICONDUCTOR INTEGRATED CIRCUIT AND APPARATUS AND METHOD OF DESIGNING SEMICONDUCTOR INTEGRATED CIRCUIT Aug 18, 2015 Abandoned
Array ( [id] => 10471218 [patent_doc_number] => 20150356235 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-10 [patent_title] => 'GENERATING A SEMICONDUCTOR COMPONENT LAYOUT' [patent_app_type] => utility [patent_app_number] => 14/830017 [patent_app_country] => US [patent_app_date] => 2015-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6361 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14830017 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/830017
Generating a semiconductor component layout Aug 18, 2015 Issued
Array ( [id] => 10801772 [patent_doc_number] => 20160147929 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-26 [patent_title] => 'METHOD OF RESOLVING MULTI-PATTERNED COLOR CONFLICTS FOR MULTI-ROW LOGIC CELLS' [patent_app_type] => utility [patent_app_number] => 14/828496 [patent_app_country] => US [patent_app_date] => 2015-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8603 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14828496 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/828496
Method of resolving multi-patterned color conflicts for multi-row logic cells Aug 16, 2015 Issued
Array ( [id] => 10801776 [patent_doc_number] => 20160147933 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-26 [patent_title] => 'METHOD OF RESOLVING COLOR CONFLICTS FOR CELL-BASED DESIGNS WITH MULTI-PATTERN LITHOGRAPHY' [patent_app_type] => utility [patent_app_number] => 14/828485 [patent_app_country] => US [patent_app_date] => 2015-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8308 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14828485 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/828485
Method of resolving color conflicts for cell-based designs with multi-pattern lithography Aug 16, 2015 Issued
Array ( [id] => 11445449 [patent_doc_number] => 20170046470 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-02-16 [patent_title] => 'PROCESS DESIGN KIT FOR EFFICIENT AND ACCURATE MISMATCH SIMULATION OF ANALOG CIRCUITS' [patent_app_type] => utility [patent_app_number] => 14/826250 [patent_app_country] => US [patent_app_date] => 2015-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4702 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14826250 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/826250
PROCESS DESIGN KIT FOR EFFICIENT AND ACCURATE MISMATCH SIMULATION OF ANALOG CIRCUITS Aug 13, 2015 Abandoned
Array ( [id] => 14176157 [patent_doc_number] => 10262094 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-16 [patent_title] => Synthesis of DC accurate noise compatible reduced netlist [patent_app_type] => utility [patent_app_number] => 14/754480 [patent_app_country] => US [patent_app_date] => 2015-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6073 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14754480 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/754480
Synthesis of DC accurate noise compatible reduced netlist Jun 28, 2015 Issued
Array ( [id] => 11094489 [patent_doc_number] => 20160291458 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-06 [patent_title] => 'METHOD INTEGRATING TARGET OPTIMIZATION AND OPTICAL PROXIMITY CORRECTION' [patent_app_type] => utility [patent_app_number] => 14/753192 [patent_app_country] => US [patent_app_date] => 2015-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3216 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14753192 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/753192
METHOD INTEGRATING TARGET OPTIMIZATION AND OPTICAL PROXIMITY CORRECTION Jun 28, 2015 Abandoned
Array ( [id] => 12146866 [patent_doc_number] => 09881119 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-01-30 [patent_title] => 'Methods, systems, and computer program product for constructing a simulation schematic of an electronic design across multiple design fabrics' [patent_app_type] => utility [patent_app_number] => 14/754535 [patent_app_country] => US [patent_app_date] => 2015-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 22 [patent_no_of_words] => 12188 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14754535 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/754535
Methods, systems, and computer program product for constructing a simulation schematic of an electronic design across multiple design fabrics Jun 28, 2015 Issued
Array ( [id] => 13680335 [patent_doc_number] => 20160378904 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-29 [patent_title] => EARLY OVERLAY PREDICTION AND OVERLAY-AWARE MASK DESIGN [patent_app_type] => utility [patent_app_number] => 14/753344 [patent_app_country] => US [patent_app_date] => 2015-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5835 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14753344 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/753344
Early overlay prediction and overlay-aware mask design Jun 28, 2015 Issued
Array ( [id] => 14825871 [patent_doc_number] => 10409945 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-09-10 [patent_title] => Methods, systems, and computer program product for connectivity verification of electronic designs [patent_app_type] => utility [patent_app_number] => 14/754331 [patent_app_country] => US [patent_app_date] => 2015-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 11253 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 299 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14754331 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/754331
Methods, systems, and computer program product for connectivity verification of electronic designs Jun 28, 2015 Issued
Array ( [id] => 11551635 [patent_doc_number] => 09620493 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-04-11 [patent_title] => 'Method of manufacturing three-dimensional semiconductor chip' [patent_app_type] => utility [patent_app_number] => 14/747519 [patent_app_country] => US [patent_app_date] => 2015-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4276 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14747519 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/747519
Method of manufacturing three-dimensional semiconductor chip Jun 22, 2015 Issued
Array ( [id] => 14331305 [patent_doc_number] => 10296673 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-05-21 [patent_title] => Mixed-language simulation [patent_app_type] => utility [patent_app_number] => 14/723188 [patent_app_country] => US [patent_app_date] => 2015-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 4829 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 277 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14723188 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/723188
Mixed-language simulation May 26, 2015 Issued
Array ( [id] => 14331353 [patent_doc_number] => 10296697 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-21 [patent_title] => Interference check system [patent_app_type] => utility [patent_app_number] => 15/314093 [patent_app_country] => US [patent_app_date] => 2015-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 36 [patent_no_of_words] => 11554 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 273 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15314093 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/314093
Interference check system May 26, 2015 Issued
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