Search

Eric D. Lee

Examiner (ID: 1963, Phone: (571)270-7098 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2851, 2825
Total Applications
773
Issued Applications
618
Pending Applications
46
Abandoned Applications
125

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10462653 [patent_doc_number] => 20150347668 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-03 [patent_title] => 'INFORMATION PROCESSING APPARATUS, METHOD, AND STORAGE MEDIUM' [patent_app_type] => utility [patent_app_number] => 14/722549 [patent_app_country] => US [patent_app_date] => 2015-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 8666 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14722549 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/722549
Information processing apparatus, method, and storage medium May 26, 2015 Issued
Array ( [id] => 10471216 [patent_doc_number] => 20150356232 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-10 [patent_title] => 'Method and System for Generating a Circuit Design, Method for Calibration of an Inspection Apparatus and Method for Process Control and Yield Management' [patent_app_type] => utility [patent_app_number] => 14/721988 [patent_app_country] => US [patent_app_date] => 2015-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4449 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14721988 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/721988
Method and System for Generating a Circuit Design, Method for Calibration of an Inspection Apparatus and Method for Process Control and Yield Management May 25, 2015 Abandoned
Array ( [id] => 10462630 [patent_doc_number] => 20150347644 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-03 [patent_title] => 'DESIGNING APPARATUS AND DESIGNING METHOD' [patent_app_type] => utility [patent_app_number] => 14/721770 [patent_app_country] => US [patent_app_date] => 2015-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 41 [patent_figures_cnt] => 41 [patent_no_of_words] => 15376 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14721770 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/721770
DESIGNING APPARATUS AND DESIGNING METHOD May 25, 2015 Abandoned
Array ( [id] => 15789645 [patent_doc_number] => 10628549 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-21 [patent_title] => Automation generation of test layouts for verifying a DRC deck [patent_app_type] => utility [patent_app_number] => 15/565882 [patent_app_country] => US [patent_app_date] => 2015-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 8051 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15565882 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/565882
Automation generation of test layouts for verifying a DRC deck Apr 14, 2015 Issued
Array ( [id] => 11598956 [patent_doc_number] => 09646126 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-05-09 [patent_title] => 'Post-routing structural netlist optimization for circuit designs' [patent_app_type] => utility [patent_app_number] => 14/671920 [patent_app_country] => US [patent_app_date] => 2015-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 16 [patent_no_of_words] => 12457 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14671920 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/671920
Post-routing structural netlist optimization for circuit designs Mar 26, 2015 Issued
Array ( [id] => 11086676 [patent_doc_number] => 20160283642 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-29 [patent_title] => 'METHOD FOR VERIFYING DESIGN RULE CHECKS' [patent_app_type] => utility [patent_app_number] => 14/669697 [patent_app_country] => US [patent_app_date] => 2015-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3964 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14669697 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/669697
Method for verifying design rule checks Mar 25, 2015 Issued
Array ( [id] => 12256170 [patent_doc_number] => 09928316 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-03-27 [patent_title] => 'Process-metrology reproducibility bands for lithographic photomasks' [patent_app_type] => utility [patent_app_number] => 14/669924 [patent_app_country] => US [patent_app_date] => 2015-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 6779 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14669924 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/669924
Process-metrology reproducibility bands for lithographic photomasks Mar 25, 2015 Issued
Array ( [id] => 11086675 [patent_doc_number] => 20160283641 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-29 [patent_title] => 'METHOD AND APPARATUS FOR IMPROVING PERFORMANCE AND POWER IN AN ELECTRONIC DESIGN USING STANDARD CELLS' [patent_app_type] => utility [patent_app_number] => 14/668687 [patent_app_country] => US [patent_app_date] => 2015-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6208 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14668687 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/668687
METHOD AND APPARATUS FOR IMPROVING PERFORMANCE AND POWER IN AN ELECTRONIC DESIGN USING STANDARD CELLS Mar 24, 2015 Abandoned
Array ( [id] => 11086674 [patent_doc_number] => 20160283640 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-29 [patent_title] => 'COLLAPSING TERMS IN STATISTICAL STATIC TIMING ANALYSIS' [patent_app_type] => utility [patent_app_number] => 14/666857 [patent_app_country] => US [patent_app_date] => 2015-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6988 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14666857 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/666857
Collapsing terms in statistical static timing analysis Mar 23, 2015 Issued
Array ( [id] => 10393408 [patent_doc_number] => 20150278415 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-01 [patent_title] => 'DESIGN METHOD AND DESIGN APPARATUS' [patent_app_type] => utility [patent_app_number] => 14/629910 [patent_app_country] => US [patent_app_date] => 2015-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6928 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14629910 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/629910
Method and design apparatus Feb 23, 2015 Issued
Array ( [id] => 11049953 [patent_doc_number] => 20160246913 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-25 [patent_title] => 'Code Coverage Reconstruction' [patent_app_type] => utility [patent_app_number] => 14/630345 [patent_app_country] => US [patent_app_date] => 2015-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7390 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14630345 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/630345
Code coverage reconstruction Feb 23, 2015 Issued
Array ( [id] => 11830938 [patent_doc_number] => 09727681 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-08-08 [patent_title] => 'Generating specific memory models using generic memory models for designing memories in VLSI design' [patent_app_type] => utility [patent_app_number] => 14/628668 [patent_app_country] => US [patent_app_date] => 2015-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5022 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14628668 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/628668
Generating specific memory models using generic memory models for designing memories in VLSI design Feb 22, 2015 Issued
Array ( [id] => 11830939 [patent_doc_number] => 09727682 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-08-08 [patent_title] => 'Designing memories in VLSI design using specific memory models generated from generic memory models' [patent_app_type] => utility [patent_app_number] => 14/628676 [patent_app_country] => US [patent_app_date] => 2015-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5022 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14628676 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/628676
Designing memories in VLSI design using specific memory models generated from generic memory models Feb 22, 2015 Issued
Array ( [id] => 10363509 [patent_doc_number] => 20150248514 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-09-03 [patent_title] => 'AUTOMATIC LAYOUT MODIFICATION TOOL WITH NON-UNIFORM GRIDS' [patent_app_type] => utility [patent_app_number] => 14/629303 [patent_app_country] => US [patent_app_date] => 2015-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 10120 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14629303 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/629303
Automatic layout modification tool with non-uniform grids Feb 22, 2015 Issued
Array ( [id] => 11049952 [patent_doc_number] => 20160246910 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-25 [patent_title] => 'Memory Optimization in VLSI Design Using Generic Memory Models' [patent_app_type] => utility [patent_app_number] => 14/628105 [patent_app_country] => US [patent_app_date] => 2015-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4980 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14628105 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/628105
Memory optimization in VLSI design using generic memory models Feb 19, 2015 Issued
Array ( [id] => 11709282 [patent_doc_number] => 20170177782 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-22 [patent_title] => 'CLASSICAL SIMULATION CONSTANTS AND ORDERING FOR QUANTUM CHEMISTRY SIMULATION' [patent_app_type] => utility [patent_app_number] => 15/118476 [patent_app_country] => US [patent_app_date] => 2015-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5076 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15118476 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/118476
Classical simulation constants and ordering for quantum chemistry simulation Feb 5, 2015 Issued
Array ( [id] => 12256185 [patent_doc_number] => 09928331 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-03-27 [patent_title] => 'Method and control device for circuit layout migration' [patent_app_type] => utility [patent_app_number] => 14/561280 [patent_app_country] => US [patent_app_date] => 2014-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 5632 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14561280 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/561280
Method and control device for circuit layout migration Dec 4, 2014 Issued
Array ( [id] => 14615259 [patent_doc_number] => 10360332 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-23 [patent_title] => Handling blind statements in mixed language environments [patent_app_type] => utility [patent_app_number] => 14/549242 [patent_app_country] => US [patent_app_date] => 2014-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5195 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14549242 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/549242
Handling blind statements in mixed language environments Nov 19, 2014 Issued
Array ( [id] => 10702481 [patent_doc_number] => 20160048628 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-18 [patent_title] => 'METHOD FOR DYNAMIC EXPERIMENTAL DESIGN' [patent_app_type] => utility [patent_app_number] => 14/547731 [patent_app_country] => US [patent_app_date] => 2014-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3338 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14547731 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/547731
METHOD FOR DYNAMIC EXPERIMENTAL DESIGN Nov 18, 2014 Abandoned
Array ( [id] => 9919424 [patent_doc_number] => 20150074629 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-12 [patent_title] => 'PARASITIC COMPONENT LIBRARY AND METHOD FOR EFFICIENT CIRCUIT DESIGN AND SIMULATION USING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/542690 [patent_app_country] => US [patent_app_date] => 2014-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4938 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14542690 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/542690
Parasitic component library and method for efficient circuit design and simulation using the same Nov 16, 2014 Issued
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