Eric D. Lee

Array ( [id] => 10778958 [patent_doc_number] => 20160125114 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-05 [patent_title] => 'METHOD AND APPARATUS FOR BITCELL MODELING' [patent_app_type] => utility [patent_app_number] => 14/531451 [patent_app_country] => US [patent_app_date] => 2014-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2708 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14531451 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14604625 [patent_doc_number] => 10355511 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-16 [patent_title] => Mobile-terminal charging device and vehicle equipped with same [patent_app_type] => utility [patent_app_number] => 15/027729 [patent_app_country] => US [patent_app_date] => 2014-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 24 [patent_no_of_words] => 7134 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 332 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15027729 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11411006 [patent_doc_number] => 09558311 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-01-31 [patent_title] => 'Surface region selection for heat sink placement' [patent_app_type] => utility [patent_app_number] => 14/525292 [patent_app_country] => US [patent_app_date] => 2014-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 9819 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14525292 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11473421 [patent_doc_number] => 20170060204 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-02 [patent_title] => 'AUTOMATIC GENERATION OF POWER MANAGEMENT SEQUENCE IN A SOC OR NOC' [patent_app_type] => utility [patent_app_number] => 14/498907 [patent_app_country] => US [patent_app_date] => 2014-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 9746 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14498907 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10210879 [patent_doc_number] => 20150095871 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-02 [patent_title] => 'CIRCUIT DESIGN SUPPORT METHOD, COMPUTER PRODUCT, CIRCUIT DESIGN SUPPORT APPARATUS, AND SEMICONDUCTOR INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 14/497876 [patent_app_country] => US [patent_app_date] => 2014-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 34 [patent_no_of_words] => 11288 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14497876 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10210873 [patent_doc_number] => 20150095865 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-02 [patent_title] => 'Legalizing a Multi-patterning Integrated Circuit Layout' [patent_app_type] => utility [patent_app_number] => 14/498663 [patent_app_country] => US [patent_app_date] => 2014-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8626 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14498663 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10432414 [patent_doc_number] => 20150317426 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-11-05 [patent_title] => 'DATA PATH SYSTEM ON CHIP DESIGN METHODOLOGY' [patent_app_type] => utility [patent_app_number] => 14/498939 [patent_app_country] => US [patent_app_date] => 2014-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 8894 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14498939 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11046999 [patent_doc_number] => 20160243957 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-25 [patent_title] => 'METHOD FOR MINIMIZING CELL AGING OF A BATTERY AND/OR BATTERY COMPRISING AN APPARATUS FOR MINIMIZING CELL AGING OF THE BATTERY' [patent_app_type] => utility [patent_app_number] => 15/027553 [patent_app_country] => US [patent_app_date] => 2014-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3434 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15027553 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10105972 [patent_doc_number] => 09141754 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-09-22 [patent_title] => 'Generating a semiconductor component layout' [patent_app_type] => utility [patent_app_number] => 14/489155 [patent_app_country] => US [patent_app_date] => 2014-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6507 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 29 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14489155 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10144281 [patent_doc_number] => 09177090 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-11-03 [patent_title] => 'In-hierarchy circuit analysis and modification for circuit instances' [patent_app_type] => utility [patent_app_number] => 14/483040 [patent_app_country] => US [patent_app_date] => 2014-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 5788 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 4 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14483040 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11931845 [patent_doc_number] => 09798845 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-10-24 [patent_title] => 'User grey cell' [patent_app_type] => utility [patent_app_number] => 14/478452 [patent_app_country] => US [patent_app_date] => 2014-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 18 [patent_no_of_words] => 13189 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14478452 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10501648 [patent_doc_number] => 09230049 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-01-05 [patent_title] => 'Arraying power grid vias by tile cells' [patent_app_type] => utility [patent_app_number] => 14/478083 [patent_app_country] => US [patent_app_date] => 2014-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4388 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 244 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14478083 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13016629 [patent_doc_number] => 10031429 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-24 [patent_title] => Method of obtaining position, exposure method, and method of manufacturing article [patent_app_type] => utility [patent_app_number] => 14/477477 [patent_app_country] => US [patent_app_date] => 2014-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 22 [patent_no_of_words] => 10893 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14477477 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10583009 [patent_doc_number] => 09305133 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-04-05 [patent_title] => 'System and method for selective application and reconciliation of hierarchical ordered sets of circuit design constraints within a circuit design editor' [patent_app_type] => utility [patent_app_number] => 14/476807 [patent_app_country] => US [patent_app_date] => 2014-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 13027 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 297 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14476807 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10188361 [patent_doc_number] => 09217774 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-12-22 [patent_title] => 'Cycle-accurate replay and debugging of running FPGA systems' [patent_app_type] => utility [patent_app_number] => 14/473058 [patent_app_country] => US [patent_app_date] => 2014-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 8387 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14473058 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11482543 [patent_doc_number] => 09589090 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-03-07 [patent_title] => 'Method and apparatus for performing multiple stage physical synthesis' [patent_app_type] => utility [patent_app_number] => 14/466610 [patent_app_country] => US [patent_app_date] => 2014-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7352 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14466610 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11523718 [patent_doc_number] => 09607121 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-03-28 [patent_title] => 'Cascode CMOS structure' [patent_app_type] => utility [patent_app_number] => 14/464730 [patent_app_country] => US [patent_app_date] => 2014-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 2880 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14464730 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9903613 [patent_doc_number] => 20150058813 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-02-26 [patent_title] => 'MULTI-MODEL METROLOGY' [patent_app_type] => utility [patent_app_number] => 14/459516 [patent_app_country] => US [patent_app_date] => 2014-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6795 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14459516 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10215936 [patent_doc_number] => 20150100929 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-09 [patent_title] => 'REVERSE SYNTHESIS OF DIGITAL NETLISTS' [patent_app_type] => utility [patent_app_number] => 14/454343 [patent_app_country] => US [patent_app_date] => 2014-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3522 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14454343 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9912419 [patent_doc_number] => 20150067623 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-05 [patent_title] => 'TIMING ANALYSIS METHOD FOR NON-STANDARD CELL CIRCUIT AND ASSOCIATED MACHINE READABLE MEDIUM' [patent_app_type] => utility [patent_app_number] => 14/450279 [patent_app_country] => US [patent_app_date] => 2014-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1768 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14450279 [rel_patent_id] =>[rel_patent_doc_number] =>)