Search

Eric D. Lee

Examiner (ID: 1963, Phone: (571)270-7098 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2851, 2825
Total Applications
773
Issued Applications
618
Pending Applications
46
Abandoned Applications
125

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11523718 [patent_doc_number] => 09607121 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-03-28 [patent_title] => 'Cascode CMOS structure' [patent_app_type] => utility [patent_app_number] => 14/464730 [patent_app_country] => US [patent_app_date] => 2014-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 2880 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14464730 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/464730
Cascode CMOS structure Aug 20, 2014 Issued
Array ( [id] => 9903613 [patent_doc_number] => 20150058813 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-02-26 [patent_title] => 'MULTI-MODEL METROLOGY' [patent_app_type] => utility [patent_app_number] => 14/459516 [patent_app_country] => US [patent_app_date] => 2014-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6795 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14459516 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/459516
Multi-model metrology Aug 13, 2014 Issued
Array ( [id] => 10215936 [patent_doc_number] => 20150100929 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-09 [patent_title] => 'REVERSE SYNTHESIS OF DIGITAL NETLISTS' [patent_app_type] => utility [patent_app_number] => 14/454343 [patent_app_country] => US [patent_app_date] => 2014-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3522 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14454343 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/454343
REVERSE SYNTHESIS OF DIGITAL NETLISTS Aug 6, 2014 Abandoned
Array ( [id] => 9912419 [patent_doc_number] => 20150067623 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-05 [patent_title] => 'TIMING ANALYSIS METHOD FOR NON-STANDARD CELL CIRCUIT AND ASSOCIATED MACHINE READABLE MEDIUM' [patent_app_type] => utility [patent_app_number] => 14/450279 [patent_app_country] => US [patent_app_date] => 2014-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1768 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14450279 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/450279
TIMING ANALYSIS METHOD FOR NON-STANDARD CELL CIRCUIT AND ASSOCIATED MACHINE READABLE MEDIUM Aug 2, 2014 Abandoned
Array ( [id] => 10178076 [patent_doc_number] => 09208282 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-12-08 [patent_title] => 'Enabling IP execution on a simulation execution platform' [patent_app_type] => utility [patent_app_number] => 14/447439 [patent_app_country] => US [patent_app_date] => 2014-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 4597 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14447439 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/447439
Enabling IP execution on a simulation execution platform Jul 29, 2014 Issued
Array ( [id] => 10052707 [patent_doc_number] => 09092587 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-07-28 [patent_title] => 'Congestion estimation techniques at pre-synthesis stage' [patent_app_type] => utility [patent_app_number] => 14/446536 [patent_app_country] => US [patent_app_date] => 2014-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5016 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 247 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14446536 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/446536
Congestion estimation techniques at pre-synthesis stage Jul 29, 2014 Issued
Array ( [id] => 10934792 [patent_doc_number] => 20140337812 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-11-13 [patent_title] => 'CIRCUIT VERIFICATION METHOD AND CIRCUIT VERIFICATION APPARATUS' [patent_app_type] => utility [patent_app_number] => 14/340029 [patent_app_country] => US [patent_app_date] => 2014-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 8922 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14340029 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/340029
CIRCUIT VERIFICATION METHOD AND CIRCUIT VERIFICATION APPARATUS Jul 23, 2014 Abandoned
Array ( [id] => 10679663 [patent_doc_number] => 20160025807 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-01-28 [patent_title] => 'SYSTEMS AND METHODS FOR WAFER-LEVEL LOOPBACK TEST' [patent_app_type] => utility [patent_app_number] => 14/339224 [patent_app_country] => US [patent_app_date] => 2014-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5980 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14339224 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/339224
Systems and methods for wafer-level loopback test Jul 22, 2014 Issued
Array ( [id] => 10666022 [patent_doc_number] => 20160012167 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-01-14 [patent_title] => 'ELIMINATION OF ILLEGAL STATES WITHIN EQUIVALENCE CHECKING' [patent_app_type] => utility [patent_app_number] => 14/329494 [patent_app_country] => US [patent_app_date] => 2014-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9104 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14329494 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/329494
Elimination of illegal states within equivalence checking Jul 10, 2014 Issued
Array ( [id] => 11791233 [patent_doc_number] => 09400864 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-07-26 [patent_title] => 'System and method for maintaining slack continuity in incremental statistical timing analysis' [patent_app_type] => utility [patent_app_number] => 14/326488 [patent_app_country] => US [patent_app_date] => 2014-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 3850 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14326488 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/326488
System and method for maintaining slack continuity in incremental statistical timing analysis Jul 8, 2014 Issued
Array ( [id] => 11775385 [patent_doc_number] => 09384316 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-07-05 [patent_title] => 'Path-based congestion reduction in integrated circuit routing' [patent_app_type] => utility [patent_app_number] => 14/326832 [patent_app_country] => US [patent_app_date] => 2014-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7472 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 466 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14326832 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/326832
Path-based congestion reduction in integrated circuit routing Jul 8, 2014 Issued
Array ( [id] => 10301592 [patent_doc_number] => 20150186592 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-02 [patent_title] => 'METHOD FOR DESIGNING PHOTOMASK AND COMPUTER READABLE RECORDING MEDIUM RECORDED WITH PHOTOMASK DESIGN PROGRAM' [patent_app_type] => utility [patent_app_number] => 14/326445 [patent_app_country] => US [patent_app_date] => 2014-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7576 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14326445 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/326445
METHOD FOR DESIGNING PHOTOMASK AND COMPUTER READABLE RECORDING MEDIUM RECORDED WITH PHOTOMASK DESIGN PROGRAM Jul 7, 2014 Abandoned
Array ( [id] => 11003259 [patent_doc_number] => 20160200208 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-07-14 [patent_title] => 'SYSTEM FOR CHARGING AN ELECTRIC VEHICLE, ELECTRIC VEHICLE AND METHOD' [patent_app_type] => utility [patent_app_number] => 14/917180 [patent_app_country] => US [patent_app_date] => 2014-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6348 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14917180 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/917180
System for charging an electric vehicle, electric vehicle and method Jul 2, 2014 Issued
Array ( [id] => 11359381 [patent_doc_number] => 09536036 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-01-03 [patent_title] => 'In-hierarchy circuit analysis and modification' [patent_app_type] => utility [patent_app_number] => 14/313875 [patent_app_country] => US [patent_app_date] => 2014-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 3978 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14313875 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/313875
In-hierarchy circuit analysis and modification Jun 23, 2014 Issued
Array ( [id] => 10958714 [patent_doc_number] => 20140361739 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-12-11 [patent_title] => 'WIRELESS POWER TRANSFER METHOD, WIRELESS POWER TRANSMITTER AND WIRELESS CHARGING SYSTEM' [patent_app_type] => utility [patent_app_number] => 14/301032 [patent_app_country] => US [patent_app_date] => 2014-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 19835 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14301032 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/301032
Wireless power transmitter, wireless power receiver and wireless charging system in home appliances Jun 9, 2014 Issued
Array ( [id] => 10623704 [patent_doc_number] => 09342648 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-05-17 [patent_title] => 'Optical proximity correction (OPC) accounting for critical dimension (CD) variation from inter-level effects' [patent_app_type] => utility [patent_app_number] => 14/301010 [patent_app_country] => US [patent_app_date] => 2014-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4852 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14301010 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/301010
Optical proximity correction (OPC) accounting for critical dimension (CD) variation from inter-level effects Jun 9, 2014 Issued
Array ( [id] => 10610190 [patent_doc_number] => 09330225 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-05-03 [patent_title] => 'Photomask error correction' [patent_app_type] => utility [patent_app_number] => 14/296705 [patent_app_country] => US [patent_app_date] => 2014-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 7027 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 295 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14296705 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/296705
Photomask error correction Jun 4, 2014 Issued
Array ( [id] => 11769640 [patent_doc_number] => 09378309 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-06-28 [patent_title] => 'Pattern-independent and hybrid matching/tuning including light manipulation by projection optics' [patent_app_type] => utility [patent_app_number] => 14/294745 [patent_app_country] => US [patent_app_date] => 2014-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 12410 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14294745 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/294745
Pattern-independent and hybrid matching/tuning including light manipulation by projection optics Jun 2, 2014 Issued
Array ( [id] => 10462327 [patent_doc_number] => 20150347342 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-03 [patent_title] => 'TERMINAL BOARD ARCHITECTURE FOR UNIVERSAL I/O ALLOWING SIMPLEX OR REDUNDANT DEVICES' [patent_app_type] => utility [patent_app_number] => 14/294628 [patent_app_country] => US [patent_app_date] => 2014-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 2766 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14294628 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/294628
TERMINAL BOARD ARCHITECTURE FOR UNIVERSAL I/O ALLOWING SIMPLEX OR REDUNDANT DEVICES Jun 2, 2014 Abandoned
Array ( [id] => 9746575 [patent_doc_number] => 20140282294 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-18 [patent_title] => 'METHOD, SYSTEM AND SOFTWARE FOR ACCESSING DESIGN RULES AND LIBRARY OF DESIGN FEATURES WHILE DESIGNING SEMICONDUCTOR DEVICE LAYOUT' [patent_app_type] => utility [patent_app_number] => 14/289256 [patent_app_country] => US [patent_app_date] => 2014-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4378 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14289256 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/289256
Method, system and software for accessing design rules and library of design features while designing semiconductor device layout May 27, 2014 Issued
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