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Eric D. Lee

Examiner (ID: 17546)

Most Active Art Unit
2851
Art Unit(s)
2851, 2825
Total Applications
769
Issued Applications
617
Pending Applications
44
Abandoned Applications
124

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20507360 [patent_doc_number] => 12541637 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-03 [patent_title] => Reinforcement learning based correction of timing failures [patent_app_type] => utility [patent_app_number] => 18/063408 [patent_app_country] => US [patent_app_date] => 2022-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 4620 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18063408 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/063408
Reinforcement learning based correction of timing failures Dec 7, 2022 Issued
Array ( [id] => 20507360 [patent_doc_number] => 12541637 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-03 [patent_title] => Reinforcement learning based correction of timing failures [patent_app_type] => utility [patent_app_number] => 18/063408 [patent_app_country] => US [patent_app_date] => 2022-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 4620 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18063408 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/063408
Reinforcement learning based correction of timing failures Dec 7, 2022 Issued
Array ( [id] => 18471820 [patent_doc_number] => 20230206106 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-29 [patent_title] => OPTICAL CIRCUITS FOR PURIFICATION OF SINGLE PHOTON STATES [patent_app_type] => utility [patent_app_number] => 18/077863 [patent_app_country] => US [patent_app_date] => 2022-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14567 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18077863 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/077863
OPTICAL CIRCUITS FOR PURIFICATION OF SINGLE PHOTON STATES Dec 7, 2022 Pending
Array ( [id] => 18438712 [patent_doc_number] => 20230186007 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-15 [patent_title] => SYSTEM AND METHOD FOR OPTIMIZING INTEGRATED CIRCUIT LAYOUT BASED ON NEURAL NETWORK [patent_app_type] => utility [patent_app_number] => 18/062922 [patent_app_country] => US [patent_app_date] => 2022-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10080 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 323 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18062922 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/062922
System and method for optimizing integrated circuit layout based on neural network Dec 6, 2022 Issued
Array ( [id] => 19220267 [patent_doc_number] => 20240184971 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-06 [patent_title] => BIT LINE ALIGNMENT FOR THE REDUCTION OF SOFT ERRORS [patent_app_type] => utility [patent_app_number] => 18/062098 [patent_app_country] => US [patent_app_date] => 2022-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7034 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18062098 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/062098
BIT LINE ALIGNMENT FOR THE REDUCTION OF SOFT ERRORS Dec 5, 2022 Pending
Array ( [id] => 20215348 [patent_doc_number] => 12412002 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-09 [patent_title] => Systems and methods for adding a design element to a design [patent_app_type] => utility [patent_app_number] => 17/994376 [patent_app_country] => US [patent_app_date] => 2022-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 7351 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17994376 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/994376
Systems and methods for adding a design element to a design Nov 26, 2022 Issued
Array ( [id] => 18454700 [patent_doc_number] => 20230195980 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-22 [patent_title] => Integrated Circuit Generation Using an Integrated Circuit Shell [patent_app_type] => utility [patent_app_number] => 17/992976 [patent_app_country] => US [patent_app_date] => 2022-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11086 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17992976 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/992976
Integrated circuit generation using an integrated circuit shell Nov 22, 2022 Issued
Array ( [id] => 18407893 [patent_doc_number] => 20230169246 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-01 [patent_title] => INTERACTIVE COMPACTION TOOL FOR ELECTRONIC DESIGN AUTOMATION [patent_app_type] => utility [patent_app_number] => 17/992876 [patent_app_country] => US [patent_app_date] => 2022-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 23500 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17992876 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/992876
INTERACTIVE COMPACTION TOOL FOR ELECTRONIC DESIGN AUTOMATION Nov 21, 2022 Pending
Array ( [id] => 18513601 [patent_doc_number] => 20230229836 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-20 [patent_title] => GENERATING AND DISPLAY AN ANIMATION OF A PREDICTED OVERLAP SHAPE IN AN IC DESIGN [patent_app_type] => utility [patent_app_number] => 17/992907 [patent_app_country] => US [patent_app_date] => 2022-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12476 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17992907 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/992907
Generating and display an animation of a predicted overlap shape in an IC design Nov 21, 2022 Issued
Array ( [id] => 18577951 [patent_doc_number] => 11734484 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-22 [patent_title] => Method for automating semiconductor design based on artificial intelligence [patent_app_type] => utility [patent_app_number] => 17/986167 [patent_app_country] => US [patent_app_date] => 2022-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 21 [patent_no_of_words] => 16144 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17986167 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/986167
Method for automating semiconductor design based on artificial intelligence Nov 13, 2022 Issued
Array ( [id] => 19144955 [patent_doc_number] => 20240143891 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-02 [patent_title] => MULTI-PATH ROUTING IN A NETWORK ON CHIP [patent_app_type] => utility [patent_app_number] => 17/979649 [patent_app_country] => US [patent_app_date] => 2022-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6603 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17979649 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/979649
MULTI-PATH ROUTING IN A NETWORK ON CHIP Nov 1, 2022 Pending
Array ( [id] => 19144941 [patent_doc_number] => 20240143877 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-02 [patent_title] => EFFICIENT DELAY CALCULATIONS IN REPLICATED DESIGNS [patent_app_type] => utility [patent_app_number] => 17/978002 [patent_app_country] => US [patent_app_date] => 2022-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6050 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17978002 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/978002
Efficient delay calculations in replicated designs Oct 30, 2022 Issued
Array ( [id] => 18212550 [patent_doc_number] => 20230058814 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-23 [patent_title] => System and Method for Improving Design Performance Through Placement of Functional and Spare Cells by Leveraging LDE Effect [patent_app_type] => utility [patent_app_number] => 17/974585 [patent_app_country] => US [patent_app_date] => 2022-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6584 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17974585 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/974585
System and method for improving design performance through placement of functional and spare cells by leveraging LDE effect Oct 26, 2022 Issued
Array ( [id] => 19303902 [patent_doc_number] => 20240232482 [patent_country] => US [patent_kind] => A9 [patent_issue_date] => 2024-07-11 [patent_title] => ADAPTABLE FRAMEWORK FOR CIRCUIT DESIGN SIMULATION VERIFICATION [patent_app_type] => utility [patent_app_number] => 18/049585 [patent_app_country] => US [patent_app_date] => 2022-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7526 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18049585 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/049585
ADAPTABLE FRAMEWORK FOR CIRCUIT DESIGN SIMULATION VERIFICATION Oct 24, 2022 Pending
Array ( [id] => 19303902 [patent_doc_number] => 20240232482 [patent_country] => US [patent_kind] => A9 [patent_issue_date] => 2024-07-11 [patent_title] => ADAPTABLE FRAMEWORK FOR CIRCUIT DESIGN SIMULATION VERIFICATION [patent_app_type] => utility [patent_app_number] => 18/049585 [patent_app_country] => US [patent_app_date] => 2022-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7526 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18049585 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/049585
ADAPTABLE FRAMEWORK FOR CIRCUIT DESIGN SIMULATION VERIFICATION Oct 23, 2022 Pending
Array ( [id] => 18228884 [patent_doc_number] => 20230067878 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => METHOD AND SYSTEM FOR SOLVING THE LAGRANGIAN DUAL OF A CONSTRAINED BINARY QUADRATIC PROGRAMMING PROBLEM USING A QUANTUM ANNEALER [patent_app_type] => utility [patent_app_number] => 18/047981 [patent_app_country] => US [patent_app_date] => 2022-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10374 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18047981 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/047981
Method and system for solving the lagrangian dual of a constrained binary quadratic programming problem using a quantum annealer Oct 18, 2022 Issued
Array ( [id] => 19182667 [patent_doc_number] => 11989256 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-21 [patent_title] => Method and system for solving the Lagrangian dual of a constrained binary quadratic programming problem using a quantum annealer [patent_app_type] => utility [patent_app_number] => 18/047882 [patent_app_country] => US [patent_app_date] => 2022-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8854 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18047882 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/047882
Method and system for solving the Lagrangian dual of a constrained binary quadratic programming problem using a quantum annealer Oct 18, 2022 Issued
Array ( [id] => 18326335 [patent_doc_number] => 20230124463 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-20 [patent_title] => APPARATUS FOR AUTOMATICALLY DETERMINING VEHICLE ELECTRONIC CIRCUIT DIAGRAM [patent_app_type] => utility [patent_app_number] => 17/956256 [patent_app_country] => US [patent_app_date] => 2022-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5337 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17956256 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/956256
Apparatus for automatically determining vehicle electronic circuit diagram Sep 28, 2022 Issued
Array ( [id] => 18271423 [patent_doc_number] => 20230092665 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-23 [patent_title] => USING A MACHINE-TRAINED NETWORK TO PERFORM PHYSICAL DESIGN [patent_app_type] => utility [patent_app_number] => 17/950080 [patent_app_country] => US [patent_app_date] => 2022-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10857 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17950080 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/950080
USING A MACHINE-TRAINED NETWORK TO PERFORM PHYSICAL DESIGN Sep 20, 2022 Pending
Array ( [id] => 19841855 [patent_doc_number] => 12254245 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-18 [patent_title] => Method of processing digitalized drawing data and computer program [patent_app_type] => utility [patent_app_number] => 18/279469 [patent_app_country] => US [patent_app_date] => 2022-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5920 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 255 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18279469 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/279469
Method of processing digitalized drawing data and computer program Sep 14, 2022 Issued
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