Search

Eric D. Lee

Examiner (ID: 1963, Phone: (571)270-7098 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2851, 2825
Total Applications
773
Issued Applications
618
Pending Applications
46
Abandoned Applications
125

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9381377 [patent_doc_number] => 20140084858 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-03-27 [patent_title] => 'WIRELESS POWER TRANSMISSION APPARATUS AND METHOD AND WIRELESS POWER RECEPTION APPARATUS' [patent_app_type] => utility [patent_app_number] => 14/025516 [patent_app_country] => US [patent_app_date] => 2013-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 17028 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14025516 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/025516
Wireless power transmission apparatus and method and wireless power reception apparatus Sep 11, 2013 Issued
Array ( [id] => 10584313 [patent_doc_number] => 09306443 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-04-05 [patent_title] => 'Analog photovoltaic power circuit with auto zero calibration' [patent_app_type] => utility [patent_app_number] => 14/023900 [patent_app_country] => US [patent_app_date] => 2013-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 29 [patent_no_of_words] => 9960 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 301 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14023900 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/023900
Analog photovoltaic power circuit with auto zero calibration Sep 10, 2013 Issued
Array ( [id] => 9566448 [patent_doc_number] => 20140184161 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-03 [patent_title] => 'SOLID-STATE ACTIVE SWITCH MATRIX FOR HIGH ENERGY, MODERATE POWER BATTERY SYSTEMS' [patent_app_type] => utility [patent_app_number] => 14/023394 [patent_app_country] => US [patent_app_date] => 2013-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4905 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14023394 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/023394
Solid-state active switch matrix for high energy, moderate power battery systems Sep 9, 2013 Issued
Array ( [id] => 9860073 [patent_doc_number] => 20150040090 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-02-05 [patent_title] => 'DISCRETIZING GATE SIZES DURING NUMERICAL SYNTHESIS' [patent_app_type] => utility [patent_app_number] => 14/016010 [patent_app_country] => US [patent_app_date] => 2013-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7693 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14016010 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/016010
Discretizing gate sizes during numerical synthesis Aug 29, 2013 Issued
Array ( [id] => 11245748 [patent_doc_number] => 09471792 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-10-18 [patent_title] => 'Detection arrangement' [patent_app_type] => utility [patent_app_number] => 14/010145 [patent_app_country] => US [patent_app_date] => 2013-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 3240 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14010145 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/010145
Detection arrangement Aug 25, 2013 Issued
Array ( [id] => 9623437 [patent_doc_number] => 08793633 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-07-29 [patent_title] => 'In-hierarchy circuit analysis and modification' [patent_app_type] => utility [patent_app_number] => 13/971666 [patent_app_country] => US [patent_app_date] => 2013-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 3936 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13971666 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/971666
In-hierarchy circuit analysis and modification Aug 19, 2013 Issued
Array ( [id] => 9332721 [patent_doc_number] => 20140059503 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-02-27 [patent_title] => 'METHOD FOR PREPARING A PATTERN TO BE PRINTED ON A PLATE OR MASK BY ELECTRON BEAM LITHOGRAPHY, CORRESPONDING PRINTED CIRCUIT DESIGN SYSTEM AND COMPUTER PROGRAM' [patent_app_type] => utility [patent_app_number] => 13/967740 [patent_app_country] => US [patent_app_date] => 2013-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4106 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13967740 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/967740
Method and system for preparing a pattern to be printed on a plate or mask by electron beam lithography Aug 14, 2013 Issued
Array ( [id] => 10885704 [patent_doc_number] => 08910109 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-12-09 [patent_title] => 'System level tools to support FPGA partial reconfiguration' [patent_app_type] => utility [patent_app_number] => 13/964430 [patent_app_country] => US [patent_app_date] => 2013-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6393 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13964430 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/964430
System level tools to support FPGA partial reconfiguration Aug 11, 2013 Issued
Array ( [id] => 9386399 [patent_doc_number] => 20140089882 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-03-27 [patent_title] => 'COMPUTING DEVICE AND METHOD FOR MODULARIZING POWER SUPPLIES PLACED ON PCB' [patent_app_type] => utility [patent_app_number] => 13/961889 [patent_app_country] => US [patent_app_date] => 2013-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 1746 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13961889 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/961889
COMPUTING DEVICE AND METHOD FOR MODULARIZING POWER SUPPLIES PLACED ON PCB Aug 7, 2013 Abandoned
Array ( [id] => 9372700 [patent_doc_number] => 20140082573 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-03-20 [patent_title] => 'CIRCUIT DESIGN SUPPORT APPARATUS, CIRCUIT DESIGN SUPPORT METHOD, AND COMPUTER PRODUCT' [patent_app_type] => utility [patent_app_number] => 13/953309 [patent_app_country] => US [patent_app_date] => 2013-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7349 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13953309 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/953309
CIRCUIT DESIGN SUPPORT APPARATUS, CIRCUIT DESIGN SUPPORT METHOD, AND COMPUTER PRODUCT Jul 28, 2013 Abandoned
Array ( [id] => 11550753 [patent_doc_number] => 09619605 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-04-11 [patent_title] => 'System and method for automatically enforcing schematic layout strategy selectively applied to schematic objects' [patent_app_type] => utility [patent_app_number] => 13/949549 [patent_app_country] => US [patent_app_date] => 2013-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 21 [patent_no_of_words] => 11711 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 260 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13949549 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/949549
System and method for automatically enforcing schematic layout strategy selectively applied to schematic objects Jul 23, 2013 Issued
Array ( [id] => 13639597 [patent_doc_number] => 09846758 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-12-19 [patent_title] => Method of designing an integrated circuit and computer program product [patent_app_type] => utility [patent_app_number] => 14/899280 [patent_app_country] => US [patent_app_date] => 2013-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4230 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14899280 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/899280
Method of designing an integrated circuit and computer program product Jul 22, 2013 Issued
Array ( [id] => 10623700 [patent_doc_number] => 09342643 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-05-17 [patent_title] => 'Non-transitory computer readable medium storing timing analysis program, timing analysis device, and timing analysis method' [patent_app_type] => utility [patent_app_number] => 13/946859 [patent_app_country] => US [patent_app_date] => 2013-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 9901 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13946859 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/946859
Non-transitory computer readable medium storing timing analysis program, timing analysis device, and timing analysis method Jul 18, 2013 Issued
Array ( [id] => 9137383 [patent_doc_number] => 20130298098 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-07 [patent_title] => 'METHOD AND SYSTEM FOR HIGH SPEED AND LOW MEMORY FOOTPRINT STATIC TIMING ANALYSIS' [patent_app_type] => utility [patent_app_number] => 13/933934 [patent_app_country] => US [patent_app_date] => 2013-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2602 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13933934 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/933934
Method and system for high speed and low memory footprint static timing analysis Jul 1, 2013 Issued
Array ( [id] => 9746623 [patent_doc_number] => 20140282342 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-18 [patent_title] => 'SYSTEMS AND METHODS FOR TUNING TECHNOLOGY FILES' [patent_app_type] => utility [patent_app_number] => 13/925870 [patent_app_country] => US [patent_app_date] => 2013-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4339 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13925870 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/925870
Systems and methods for tuning technology files Jun 24, 2013 Issued
Array ( [id] => 9437640 [patent_doc_number] => 20140115547 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-04-24 [patent_title] => 'Method of Generating Parameterized Units' [patent_app_type] => utility [patent_app_number] => 13/897399 [patent_app_country] => US [patent_app_date] => 2013-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1442 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13897399 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/897399
Method of Generating Parameterized Units May 17, 2013 Abandoned
Array ( [id] => 9618430 [patent_doc_number] => 20140208287 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-24 [patent_title] => 'Energy Consumption Simulation and Evaluation System for Embedded Device' [patent_app_type] => utility [patent_app_number] => 13/856329 [patent_app_country] => US [patent_app_date] => 2013-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9008 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13856329 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/856329
Energy consumption simulation and evaluation system for embedded device Apr 2, 2013 Issued
Array ( [id] => 9746607 [patent_doc_number] => 20140282326 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-18 [patent_title] => 'Methods for Layout Verification for Polysilicon Cell Edge Structures in FinFET Standard Cells' [patent_app_type] => utility [patent_app_number] => 13/840789 [patent_app_country] => US [patent_app_date] => 2013-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7323 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13840789 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/840789
Methods for layout verification for polysilicon cell edge structures in FinFET standard cells Mar 14, 2013 Issued
Array ( [id] => 11781581 [patent_doc_number] => 09390779 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-07-12 [patent_title] => 'System and method of sensing a memory cell' [patent_app_type] => utility [patent_app_number] => 13/835251 [patent_app_country] => US [patent_app_date] => 2013-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 10937 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13835251 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/835251
System and method of sensing a memory cell Mar 14, 2013 Issued
Array ( [id] => 9746567 [patent_doc_number] => 20140282286 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-18 [patent_title] => 'ETCH FAILURE PREDICTION BASED ON WAFER RESIST TOP LOSS' [patent_app_type] => utility [patent_app_number] => 13/835339 [patent_app_country] => US [patent_app_date] => 2013-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3861 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13835339 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/835339
Etch failure prediction based on wafer resist top loss Mar 14, 2013 Issued
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