Search

Eric D. Lee

Examiner (ID: 1963, Phone: (571)270-7098 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2851, 2825
Total Applications
773
Issued Applications
618
Pending Applications
46
Abandoned Applications
125

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9746605 [patent_doc_number] => 20140282324 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-18 [patent_title] => 'PREDICTIVE 3-D VIRTUAL FABRICATION SYSTEM AND METHOD' [patent_app_type] => utility [patent_app_number] => 13/831440 [patent_app_country] => US [patent_app_date] => 2013-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 13927 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13831440 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/831440
Predictive 3-D virtual fabrication system and method Mar 13, 2013 Issued
Array ( [id] => 9163554 [patent_doc_number] => 20130311831 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-21 [patent_title] => 'VIRTUAL FAIL ADDRESS GENERATION SYSTEM, REDUNDANCY ANALYSIS SIMULATION SYSTEM, AND METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 13/790657 [patent_app_country] => US [patent_app_date] => 2013-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6837 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13790657 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/790657
VIRTUAL FAIL ADDRESS GENERATION SYSTEM, REDUNDANCY ANALYSIS SIMULATION SYSTEM, AND METHOD THEREOF Mar 7, 2013 Abandoned
Array ( [id] => 9365027 [patent_doc_number] => 20140074900 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-03-13 [patent_title] => 'ARCHITECTURE GUIDED OPTIMAL SYSTEM PRECISION DEFINITION ALGORITHM FOR CUSTOM INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 13/782927 [patent_app_country] => US [patent_app_date] => 2013-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4829 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13782927 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/782927
ARCHITECTURE GUIDED OPTIMAL SYSTEM PRECISION DEFINITION ALGORITHM FOR CUSTOM INTEGRATED CIRCUIT Feb 28, 2013 Abandoned
Array ( [id] => 9699083 [patent_doc_number] => 20140248768 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-04 [patent_title] => 'Mask Assignment Optimization' [patent_app_type] => utility [patent_app_number] => 13/781980 [patent_app_country] => US [patent_app_date] => 2013-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4273 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13781980 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/781980
Mask assignment optimization Feb 28, 2013 Issued
Array ( [id] => 9000789 [patent_doc_number] => 20130221913 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-29 [patent_title] => 'WIRELESS CHARGING DEVICE, TERMINAL, AND METHOD FOR WIRELESS CHARGING' [patent_app_type] => utility [patent_app_number] => 13/776139 [patent_app_country] => US [patent_app_date] => 2013-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 11059 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13776139 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/776139
WIRELESS CHARGING DEVICE, TERMINAL, AND METHOD FOR WIRELESS CHARGING Feb 24, 2013 Abandoned
Array ( [id] => 11246910 [patent_doc_number] => 09472961 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-10-18 [patent_title] => 'Method of forming a balancing circuit for a plurality of battery cells and structure therefor' [patent_app_type] => utility [patent_app_number] => 13/776375 [patent_app_country] => US [patent_app_date] => 2013-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 8151 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 321 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13776375 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/776375
Method of forming a balancing circuit for a plurality of battery cells and structure therefor Feb 24, 2013 Issued
Array ( [id] => 9683117 [patent_doc_number] => 20140239880 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-28 [patent_title] => 'ELECTRICAL SYSTEM, INPUT APPARATUS AND CHARGING METHOD FOR INPUT APPARATUS' [patent_app_type] => utility [patent_app_number] => 13/775260 [patent_app_country] => US [patent_app_date] => 2013-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2847 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13775260 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/775260
Electrical system, input apparatus and charging method for input apparatus Feb 24, 2013 Issued
Array ( [id] => 9092595 [patent_doc_number] => 20130271906 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-17 [patent_title] => 'Portable Power Supply' [patent_app_type] => utility [patent_app_number] => 13/774880 [patent_app_country] => US [patent_app_date] => 2013-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2668 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13774880 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/774880
Portable power supply Feb 21, 2013 Issued
Array ( [id] => 9214113 [patent_doc_number] => 20140013290 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-09 [patent_title] => 'Input Space Reduction for Verification Test Set Generation' [patent_app_type] => utility [patent_app_number] => 13/755639 [patent_app_country] => US [patent_app_date] => 2013-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7841 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13755639 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/755639
Input space reduction for verification test set generation Jan 30, 2013 Issued
Array ( [id] => 9571897 [patent_doc_number] => 20140189611 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-03 [patent_title] => 'Method Of Decomposable Checking Approach For Mask Alignment In Multiple Patterning' [patent_app_type] => utility [patent_app_number] => 13/732855 [patent_app_country] => US [patent_app_date] => 2013-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6534 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13732855 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/732855
Method of decomposable checking approach for mask alignment in multiple patterning Jan 1, 2013 Issued
Array ( [id] => 9961421 [patent_doc_number] => 09009646 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-04-14 [patent_title] => 'Finding I/O placement with a router' [patent_app_type] => utility [patent_app_number] => 13/731865 [patent_app_country] => US [patent_app_date] => 2012-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7600 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13731865 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/731865
Finding I/O placement with a router Dec 30, 2012 Issued
Array ( [id] => 10847880 [patent_doc_number] => 08875082 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-10-28 [patent_title] => 'System and method for detecting and prescribing physical corrections for timing violations in pruned timing data for electronic circuit design defined by physical implementation data' [patent_app_type] => utility [patent_app_number] => 13/729665 [patent_app_country] => US [patent_app_date] => 2012-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 25 [patent_no_of_words] => 16736 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 264 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13729665 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/729665
System and method for detecting and prescribing physical corrections for timing violations in pruned timing data for electronic circuit design defined by physical implementation data Dec 27, 2012 Issued
Array ( [id] => 9571910 [patent_doc_number] => 20140189623 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-03 [patent_title] => 'PARASITIC COMPONENT LIBRARY AND METHOD FOR EFFICIENT CIRCUIT DESIGN AND SIMULATION USING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/728295 [patent_app_country] => US [patent_app_date] => 2012-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4888 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13728295 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/728295
Parasitic component library and method for efficient circuit design and simulation using the same Dec 26, 2012 Issued
Array ( [id] => 11724136 [patent_doc_number] => 09696991 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-07-04 [patent_title] => 'Fixed-point and floating-point optimization' [patent_app_type] => utility [patent_app_number] => 13/727835 [patent_app_country] => US [patent_app_date] => 2012-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 6585 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13727835 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/727835
Fixed-point and floating-point optimization Dec 26, 2012 Issued
Array ( [id] => 9563889 [patent_doc_number] => 20140181602 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-26 [patent_title] => 'MODELING MEMORY ARRAYS FOR TEST PATTERN ANALYSIS' [patent_app_type] => utility [patent_app_number] => 13/725185 [patent_app_country] => US [patent_app_date] => 2012-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3627 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13725185 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/725185
MODELING MEMORY ARRAYS FOR TEST PATTERN ANALYSIS Dec 20, 2012 Abandoned
Array ( [id] => 8918223 [patent_doc_number] => 20130179847 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-07-11 [patent_title] => 'Source Mask Optimization to Reduce Stochastic Effects' [patent_app_type] => utility [patent_app_number] => 13/719135 [patent_app_country] => US [patent_app_date] => 2012-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 16464 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13719135 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/719135
Source mask optimization to reduce stochastic effects Dec 17, 2012 Issued
Array ( [id] => 9548898 [patent_doc_number] => 20140173546 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-19 [patent_title] => 'Method and system to view and analyze state model transition on host/semiconductor equipment for 300mm standards' [patent_app_type] => utility [patent_app_number] => 13/716235 [patent_app_country] => US [patent_app_date] => 2012-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3010 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13716235 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/716235
Method and system to view and analyze state model transition on host/semiconductor equipment for 300mm standards Dec 16, 2012 Abandoned
Array ( [id] => 10550552 [patent_doc_number] => 09275178 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-03-01 [patent_title] => 'Method and apparatus for considering paths influenced by different power supply domains in timing analysis' [patent_app_type] => utility [patent_app_number] => 13/715259 [patent_app_country] => US [patent_app_date] => 2012-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 11317 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13715259 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/715259
Method and apparatus for considering paths influenced by different power supply domains in timing analysis Dec 13, 2012 Issued
Array ( [id] => 9520720 [patent_doc_number] => 20140157212 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-05 [patent_title] => 'Distinguishable IC Patterns with Encoded Information' [patent_app_type] => utility [patent_app_number] => 13/692845 [patent_app_country] => US [patent_app_date] => 2012-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7527 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13692845 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/692845
Distinguishable IC patterns with encoded information Dec 2, 2012 Issued
Array ( [id] => 8694791 [patent_doc_number] => 20130056799 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-03-07 [patent_title] => 'CIRCUIT SIMULATION METHOD AND SEMICONDUCTOR INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 13/667749 [patent_app_country] => US [patent_app_date] => 2012-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 11201 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13667749 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/667749
CIRCUIT SIMULATION METHOD AND SEMICONDUCTOR INTEGRATED CIRCUIT Nov 1, 2012 Abandoned
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