
Eric D. Lee
Examiner (ID: 17546)
| Most Active Art Unit | 2851 |
| Art Unit(s) | 2851, 2825 |
| Total Applications | 769 |
| Issued Applications | 617 |
| Pending Applications | 44 |
| Abandoned Applications | 124 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 9000789
[patent_doc_number] => 20130221913
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-08-29
[patent_title] => 'WIRELESS CHARGING DEVICE, TERMINAL, AND METHOD FOR WIRELESS CHARGING'
[patent_app_type] => utility
[patent_app_number] => 13/776139
[patent_app_country] => US
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[patent_effective_date] => 0000-00-00
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Array
(
[id] => 11246910
[patent_doc_number] => 09472961
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-10-18
[patent_title] => 'Method of forming a balancing circuit for a plurality of battery cells and structure therefor'
[patent_app_type] => utility
[patent_app_number] => 13/776375
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/776375 | Method of forming a balancing circuit for a plurality of battery cells and structure therefor | Feb 24, 2013 | Issued |
Array
(
[id] => 9683117
[patent_doc_number] => 20140239880
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-08-28
[patent_title] => 'ELECTRICAL SYSTEM, INPUT APPARATUS AND CHARGING METHOD FOR INPUT APPARATUS'
[patent_app_type] => utility
[patent_app_number] => 13/775260
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Array
(
[id] => 9092595
[patent_doc_number] => 20130271906
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-10-17
[patent_title] => 'Portable Power Supply'
[patent_app_type] => utility
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[patent_app_country] => US
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Array
(
[id] => 9214113
[patent_doc_number] => 20140013290
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-01-09
[patent_title] => 'Input Space Reduction for Verification Test Set Generation'
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Array
(
[id] => 9571897
[patent_doc_number] => 20140189611
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-07-03
[patent_title] => 'Method Of Decomposable Checking Approach For Mask Alignment In Multiple Patterning'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/732855 | Method of decomposable checking approach for mask alignment in multiple patterning | Jan 1, 2013 | Issued |
Array
(
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[patent_title] => 'Finding I/O placement with a router'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/731865 | Finding I/O placement with a router | Dec 30, 2012 | Issued |
Array
(
[id] => 10847880
[patent_doc_number] => 08875082
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[patent_kind] => B1
[patent_issue_date] => 2014-10-28
[patent_title] => 'System and method for detecting and prescribing physical corrections for timing violations in pruned timing data for electronic circuit design defined by physical implementation data'
[patent_app_type] => utility
[patent_app_number] => 13/729665
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/729665 | System and method for detecting and prescribing physical corrections for timing violations in pruned timing data for electronic circuit design defined by physical implementation data | Dec 27, 2012 | Issued |
Array
(
[id] => 11724136
[patent_doc_number] => 09696991
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2017-07-04
[patent_title] => 'Fixed-point and floating-point optimization'
[patent_app_type] => utility
[patent_app_number] => 13/727835
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/727835 | Fixed-point and floating-point optimization | Dec 26, 2012 | Issued |
Array
(
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[patent_issue_date] => 2014-07-03
[patent_title] => 'PARASITIC COMPONENT LIBRARY AND METHOD FOR EFFICIENT CIRCUIT DESIGN AND SIMULATION USING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 13/728295
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/728295 | Parasitic component library and method for efficient circuit design and simulation using the same | Dec 26, 2012 | Issued |
Array
(
[id] => 9563889
[patent_doc_number] => 20140181602
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-06-26
[patent_title] => 'MODELING MEMORY ARRAYS FOR TEST PATTERN ANALYSIS'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/725185 | MODELING MEMORY ARRAYS FOR TEST PATTERN ANALYSIS | Dec 20, 2012 | Abandoned |
Array
(
[id] => 8918223
[patent_doc_number] => 20130179847
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[patent_title] => 'Source Mask Optimization to Reduce Stochastic Effects'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/719135 | Source mask optimization to reduce stochastic effects | Dec 17, 2012 | Issued |
Array
(
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[patent_title] => 'Method and system to view and analyze state model transition on host/semiconductor equipment for 300mm standards'
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Array
(
[id] => 10550552
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[patent_kind] => B1
[patent_issue_date] => 2016-03-01
[patent_title] => 'Method and apparatus for considering paths influenced by different power supply domains in timing analysis'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/715259 | Method and apparatus for considering paths influenced by different power supply domains in timing analysis | Dec 13, 2012 | Issued |
Array
(
[id] => 9520720
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[patent_title] => 'Distinguishable IC Patterns with Encoded Information'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/692845 | Distinguishable IC patterns with encoded information | Dec 2, 2012 | Issued |
Array
(
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[patent_title] => 'CIRCUIT SIMULATION METHOD AND SEMICONDUCTOR INTEGRATED CIRCUIT'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/667749 | CIRCUIT SIMULATION METHOD AND SEMICONDUCTOR INTEGRATED CIRCUIT | Nov 1, 2012 | Abandoned |
Array
(
[id] => 9316883
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[patent_title] => 'IN-VEHICLE ELECTRONIC SYSTEM'
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Array
(
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[patent_issue_date] => 2014-04-17
[patent_title] => 'MULTI-FINGER TRANSISTOR LAYOUT FOR REDUCING CROSS-FINGER ELECTRIC VARIATIONS AND FOR FULLY UTILIZING AVAILABLE BREAKDOWN VOLTAGES'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/649769 | Multi-finger transistor layout for reducing cross-finger electric variations and for fully utilizing available breakdown voltages | Oct 10, 2012 | Issued |
Array
(
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[patent_title] => 'SYSTEM AND METHOD FOR REMOTE MONITORING OF CHARGING THE BATTERY OF AN ELECTRIC VEHICLE, CHARGER AND DEVICE FOR USE IN THE SYSTEM AND METHOD'
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Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/351158 | Lead storage battery system | Sep 30, 2012 | Issued |