Search

Eric D. Lee

Examiner (ID: 1963, Phone: (571)270-7098 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2851, 2825
Total Applications
773
Issued Applications
618
Pending Applications
46
Abandoned Applications
125

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9579038 [patent_doc_number] => 08769475 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-07-01 [patent_title] => 'Method, system and software for accessing design rules and library of design features while designing semiconductor device layout' [patent_app_type] => utility [patent_app_number] => 13/285528 [patent_app_country] => US [patent_app_date] => 2011-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4340 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13285528 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/285528
Method, system and software for accessing design rules and library of design features while designing semiconductor device layout Oct 30, 2011 Issued
Array ( [id] => 8769537 [patent_doc_number] => 20130097574 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-04-18 [patent_title] => 'METHOD OF ANALYTICAL PLACEMENT WITH WEIGHTED-AVERAGE WIRELENGTH MODEL' [patent_app_type] => utility [patent_app_number] => 13/275348 [patent_app_country] => US [patent_app_date] => 2011-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4247 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13275348 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/275348
Method of analytical placement with weighted-average wirelength model Oct 17, 2011 Issued
Array ( [id] => 8735421 [patent_doc_number] => 20130080990 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-03-28 [patent_title] => 'METHOD OF REDUCING POWER LEAKAGE OF INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 13/245888 [patent_app_country] => US [patent_app_date] => 2011-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3158 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13245888 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/245888
METHOD OF REDUCING POWER LEAKAGE OF INTEGRATED CIRCUIT Sep 26, 2011 Abandoned
Array ( [id] => 7722144 [patent_doc_number] => 20120011479 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-01-12 [patent_title] => 'BOOSTING TRANSISTOR PERFORMANCE WITH NON-RECTANGULAR CHANNELS' [patent_app_type] => utility [patent_app_number] => 13/237818 [patent_app_country] => US [patent_app_date] => 2011-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 11660 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0011/20120011479.pdf [firstpage_image] =>[orig_patent_app_number] => 13237818 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/237818
Boosting transistor performance with non-rectangular channels Sep 19, 2011 Issued
Array ( [id] => 9392537 [patent_doc_number] => 08689162 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-04-01 [patent_title] => 'Method and apparatus for timing closure' [patent_app_type] => utility [patent_app_number] => 13/235908 [patent_app_country] => US [patent_app_date] => 2011-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 6184 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13235908 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/235908
Method and apparatus for timing closure Sep 18, 2011 Issued
Array ( [id] => 9500266 [patent_doc_number] => 08739108 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-05-27 [patent_title] => 'Method and apparatus for implementing loop-based control in an electronic design automation tool' [patent_app_type] => utility [patent_app_number] => 13/199588 [patent_app_country] => US [patent_app_date] => 2011-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 23 [patent_no_of_words] => 6951 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13199588 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/199588
Method and apparatus for implementing loop-based control in an electronic design automation tool Sep 2, 2011 Issued
Array ( [id] => 8863733 [patent_doc_number] => 20130147436 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-13 [patent_title] => 'BATTERY PACK AND ELECTRONIC PAYMENT SYSTEM' [patent_app_type] => utility [patent_app_number] => 13/818905 [patent_app_country] => US [patent_app_date] => 2011-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4357 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13818905 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/818905
BATTERY PACK AND ELECTRONIC PAYMENT SYSTEM Aug 23, 2011 Abandoned
Array ( [id] => 8863726 [patent_doc_number] => 20130147430 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-13 [patent_title] => 'DESIGN AND PRODUCTION OF A SYSTEM FOR WIRELESSLY CHARGING THE BATTERIES OF A ROBOT' [patent_app_type] => utility [patent_app_number] => 13/818698 [patent_app_country] => US [patent_app_date] => 2011-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 1605 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13818698 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/818698
DESIGN AND PRODUCTION OF A SYSTEM FOR WIRELESSLY CHARGING THE BATTERIES OF A ROBOT Aug 18, 2011 Abandoned
Array ( [id] => 11202879 [patent_doc_number] => 09433113 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-08-30 [patent_title] => 'Charger' [patent_app_type] => utility [patent_app_number] => 13/818783 [patent_app_country] => US [patent_app_date] => 2011-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5585 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 257 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13818783 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/818783
Charger Aug 11, 2011 Issued
Array ( [id] => 11234256 [patent_doc_number] => 09461494 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-10-04 [patent_title] => 'Power storage system' [patent_app_type] => utility [patent_app_number] => 13/818336 [patent_app_country] => US [patent_app_date] => 2011-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 5819 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 265 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13818336 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/818336
Power storage system Jul 18, 2011 Issued
Array ( [id] => 8613907 [patent_doc_number] => 20130019219 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-17 [patent_title] => 'SYSTEM AND METHOD FOR HIERARCHY RECONSTRUCTION FROM FLATTENED GRAPHIC DATABASE SYSTEM LAYOUT' [patent_app_type] => utility [patent_app_number] => 13/182338 [patent_app_country] => US [patent_app_date] => 2011-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 3975 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13182338 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/182338
SYSTEM AND METHOD FOR HIERARCHY RECONSTRUCTION FROM FLATTENED GRAPHIC DATABASE SYSTEM LAYOUT Jul 12, 2011 Abandoned
Array ( [id] => 8267601 [patent_doc_number] => 20120167027 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-06-28 [patent_title] => 'ELECTRONIC DEVICE AND METHOD FOR CHECKING LAYOUT DISTANCE OF A PRINTED CIRCUIT BOARD' [patent_app_type] => utility [patent_app_number] => 13/172858 [patent_app_country] => US [patent_app_date] => 2011-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2273 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13172858 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/172858
ELECTRONIC DEVICE AND METHOD FOR CHECKING LAYOUT DISTANCE OF A PRINTED CIRCUIT BOARD Jun 29, 2011 Abandoned
Array ( [id] => 8588872 [patent_doc_number] => 20130007692 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-03 [patent_title] => 'TOOL AND METHOD FOR MODELING INTERPOSER RC COUPLINGS' [patent_app_type] => utility [patent_app_number] => 13/172248 [patent_app_country] => US [patent_app_date] => 2011-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 6181 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13172248 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/172248
Tool and method for modeling interposer RC couplings Jun 28, 2011 Issued
Array ( [id] => 8588865 [patent_doc_number] => 20130007686 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-03 [patent_title] => 'METHOD, SYSTEM AND PROGRAM STORAGE DEVICE FOR MODELING THE CAPACITANCE ASSOCIATED WITH A DIFFUSION REGION OF A SILICON-ON-INSULATOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/171528 [patent_app_country] => US [patent_app_date] => 2011-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8995 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13171528 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/171528
Method, system and program storage device for modeling the capacitance associated with a diffusion region of a silicon-on-insulator device Jun 28, 2011 Issued
Array ( [id] => 8568853 [patent_doc_number] => 20120331425 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-12-27 [patent_title] => 'MANUFACTURABILITY ENHANCEMENTS FOR GATE PATTERNING PROCESS USING POLYSILICON SUB LAYER' [patent_app_type] => utility [patent_app_number] => 13/166738 [patent_app_country] => US [patent_app_date] => 2011-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7260 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13166738 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/166738
Manufacturability enhancements for gate patterning process using polysilicon sub layer Jun 21, 2011 Issued
Array ( [id] => 8230149 [patent_doc_number] => 20120144353 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-06-07 [patent_title] => 'Method for Implementing Timing Point Engineering Change Orders in an Integrated Circuit Design Flow' [patent_app_type] => utility [patent_app_number] => 13/155854 [patent_app_country] => US [patent_app_date] => 2011-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3114 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13155854 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/155854
Method for Implementing Timing Point Engineering Change Orders in an Integrated Circuit Design Flow Jun 7, 2011 Abandoned
Array ( [id] => 7658585 [patent_doc_number] => 20110307854 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-15 [patent_title] => 'MANIPULATING PARAMETERIZED CELL DEVICES IN A CUSTOM LAYOUT DESIGN' [patent_app_type] => utility [patent_app_number] => 13/154068 [patent_app_country] => US [patent_app_date] => 2011-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 4249 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0307/20110307854.pdf [firstpage_image] =>[orig_patent_app_number] => 13154068 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/154068
Manipulating parameterized cell devices in a custom layout design Jun 5, 2011 Issued
Array ( [id] => 7574942 [patent_doc_number] => 20110270598 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-11-03 [patent_title] => 'Integrated Circuit Design and Simulation' [patent_app_type] => utility [patent_app_number] => 13/095099 [patent_app_country] => US [patent_app_date] => 2011-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6973 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0270/20110270598.pdf [firstpage_image] =>[orig_patent_app_number] => 13095099 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/095099
Integrated circuit design and simulation Apr 26, 2011 Issued
Array ( [id] => 8455173 [patent_doc_number] => 20120266119 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-10-18 [patent_title] => 'Delay Model Construction In The Presence Of Multiple Input Switching Events' [patent_app_type] => utility [patent_app_number] => 13/088688 [patent_app_country] => US [patent_app_date] => 2011-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5881 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13088688 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/088688
Delay model construction in the presence of multiple input switching events Apr 17, 2011 Issued
Array ( [id] => 8455178 [patent_doc_number] => 20120266124 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-10-18 [patent_title] => 'Placement of Structured Nets' [patent_app_type] => utility [patent_app_number] => 13/086428 [patent_app_country] => US [patent_app_date] => 2011-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 10630 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13086428 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/086428
Placement of structured nets Apr 13, 2011 Issued
Menu