Eric D. Lee

Array ( [id] => 11234256 [patent_doc_number] => 09461494 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-10-04 [patent_title] => 'Power storage system' [patent_app_type] => utility [patent_app_number] => 13/818336 [patent_app_country] => US [patent_app_date] => 2011-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 5819 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 265 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13818336 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8613907 [patent_doc_number] => 20130019219 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-17 [patent_title] => 'SYSTEM AND METHOD FOR HIERARCHY RECONSTRUCTION FROM FLATTENED GRAPHIC DATABASE SYSTEM LAYOUT' [patent_app_type] => utility [patent_app_number] => 13/182338 [patent_app_country] => US [patent_app_date] => 2011-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 3975 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13182338 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8267601 [patent_doc_number] => 20120167027 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-06-28 [patent_title] => 'ELECTRONIC DEVICE AND METHOD FOR CHECKING LAYOUT DISTANCE OF A PRINTED CIRCUIT BOARD' [patent_app_type] => utility [patent_app_number] => 13/172858 [patent_app_country] => US [patent_app_date] => 2011-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2273 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13172858 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8588872 [patent_doc_number] => 20130007692 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-03 [patent_title] => 'TOOL AND METHOD FOR MODELING INTERPOSER RC COUPLINGS' [patent_app_type] => utility [patent_app_number] => 13/172248 [patent_app_country] => US [patent_app_date] => 2011-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 6181 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13172248 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8588865 [patent_doc_number] => 20130007686 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-03 [patent_title] => 'METHOD, SYSTEM AND PROGRAM STORAGE DEVICE FOR MODELING THE CAPACITANCE ASSOCIATED WITH A DIFFUSION REGION OF A SILICON-ON-INSULATOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/171528 [patent_app_country] => US [patent_app_date] => 2011-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8995 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13171528 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8568853 [patent_doc_number] => 20120331425 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-12-27 [patent_title] => 'MANUFACTURABILITY ENHANCEMENTS FOR GATE PATTERNING PROCESS USING POLYSILICON SUB LAYER' [patent_app_type] => utility [patent_app_number] => 13/166738 [patent_app_country] => US [patent_app_date] => 2011-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7260 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13166738 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8230149 [patent_doc_number] => 20120144353 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-06-07 [patent_title] => 'Method for Implementing Timing Point Engineering Change Orders in an Integrated Circuit Design Flow' [patent_app_type] => utility [patent_app_number] => 13/155854 [patent_app_country] => US [patent_app_date] => 2011-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3114 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13155854 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7658585 [patent_doc_number] => 20110307854 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-15 [patent_title] => 'MANIPULATING PARAMETERIZED CELL DEVICES IN A CUSTOM LAYOUT DESIGN' [patent_app_type] => utility [patent_app_number] => 13/154068 [patent_app_country] => US [patent_app_date] => 2011-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 4249 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0307/20110307854.pdf [firstpage_image] =>[orig_patent_app_number] => 13154068 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7574942 [patent_doc_number] => 20110270598 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-11-03 [patent_title] => 'Integrated Circuit Design and Simulation' [patent_app_type] => utility [patent_app_number] => 13/095099 [patent_app_country] => US [patent_app_date] => 2011-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6973 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0270/20110270598.pdf [firstpage_image] =>[orig_patent_app_number] => 13095099 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8455173 [patent_doc_number] => 20120266119 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-10-18 [patent_title] => 'Delay Model Construction In The Presence Of Multiple Input Switching Events' [patent_app_type] => utility [patent_app_number] => 13/088688 [patent_app_country] => US [patent_app_date] => 2011-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5881 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13088688 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8455178 [patent_doc_number] => 20120266124 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-10-18 [patent_title] => 'Placement of Structured Nets' [patent_app_type] => utility [patent_app_number] => 13/086428 [patent_app_country] => US [patent_app_date] => 2011-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 10630 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13086428 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8455180 [patent_doc_number] => 20120266126 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-10-18 [patent_title] => 'SYSTEMS AND METHODS OF DESIGNING INTEGRATED CIRCUITS' [patent_app_type] => utility [patent_app_number] => 13/084748 [patent_app_country] => US [patent_app_date] => 2011-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 5710 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13084748 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7658580 [patent_doc_number] => 20110307849 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-15 [patent_title] => 'LOGICAL DESCRIPTION DIFFERENCE EXTRACTING METHOD, LOGICAL DESIGN AIDING APPARATUS, AND NON-TRANSITORY COMPUTER-READABLE STORAGE MEDIUM THEREOF' [patent_app_type] => utility [patent_app_number] => 13/074688 [patent_app_country] => US [patent_app_date] => 2011-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7563 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0307/20110307849.pdf [firstpage_image] =>[orig_patent_app_number] => 13074688 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11259854 [patent_doc_number] => 09484764 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-11-01 [patent_title] => 'Charge control device and drive load module' [patent_app_type] => utility [patent_app_number] => 14/004766 [patent_app_country] => US [patent_app_date] => 2011-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 10963 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 461 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14004766 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8395730 [patent_doc_number] => 20120233575 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-09-13 [patent_title] => 'LAYOUT METHOD FOR INTEGRATED CIRCUIT INCLUDING VIAS' [patent_app_type] => utility [patent_app_number] => 13/044578 [patent_app_country] => US [patent_app_date] => 2011-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6613 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13044578 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8899597 [patent_doc_number] => 08479131 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-07-02 [patent_title] => 'Method of determining FET source/drain wire, contact, and diffusion resistances in the presence of multiple contacts' [patent_app_type] => utility [patent_app_number] => 13/038468 [patent_app_country] => US [patent_app_date] => 2011-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 11980 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13038468 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9077640 [patent_doc_number] => 08555232 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-08 [patent_title] => 'Wire routing using virtual landing pads' [patent_app_type] => utility [patent_app_number] => 13/036308 [patent_app_country] => US [patent_app_date] => 2011-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 5416 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13036308 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6094378 [patent_doc_number] => 20110219348 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-08 [patent_title] => 'AUTOMATIC DESIGN SUPPORT APPARATUS AND METHOD' [patent_app_type] => utility [patent_app_number] => 13/036738 [patent_app_country] => US [patent_app_date] => 2011-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 13786 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0219/20110219348.pdf [firstpage_image] =>[orig_patent_app_number] => 13036738 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9855481 [patent_doc_number] => 20150035498 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-02-05 [patent_title] => 'ACTIVE CONTROL PROCEDURES FOR THE CONNECTION OF VERY CAPACITIVE LOADS USING SSPCs' [patent_app_type] => utility [patent_app_number] => 13/996423 [patent_app_country] => US [patent_app_date] => 2011-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3614 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13996423 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8372585 [patent_doc_number] => 20120221980 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-08-30 [patent_title] => 'METHOD AND SYSTEM FOR DESIGN OF ENHANCED ACCURACY PATTERNS FOR CHARGED PARTICLE BEAM LITHOGRAPHY' [patent_app_type] => utility [patent_app_number] => 13/037268 [patent_app_country] => US [patent_app_date] => 2011-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10804 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13037268 [rel_patent_id] =>[rel_patent_doc_number] =>)