Eric D. Lee

Array ( [id] => 8899597 [patent_doc_number] => 08479131 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-07-02 [patent_title] => 'Method of determining FET source/drain wire, contact, and diffusion resistances in the presence of multiple contacts' [patent_app_type] => utility [patent_app_number] => 13/038468 [patent_app_country] => US [patent_app_date] => 2011-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 11980 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13038468 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8372585 [patent_doc_number] => 20120221980 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-08-30 [patent_title] => 'METHOD AND SYSTEM FOR DESIGN OF ENHANCED ACCURACY PATTERNS FOR CHARGED PARTICLE BEAM LITHOGRAPHY' [patent_app_type] => utility [patent_app_number] => 13/037268 [patent_app_country] => US [patent_app_date] => 2011-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10804 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13037268 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6094378 [patent_doc_number] => 20110219348 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-08 [patent_title] => 'AUTOMATIC DESIGN SUPPORT APPARATUS AND METHOD' [patent_app_type] => utility [patent_app_number] => 13/036738 [patent_app_country] => US [patent_app_date] => 2011-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 13786 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0219/20110219348.pdf [firstpage_image] =>[orig_patent_app_number] => 13036738 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9855481 [patent_doc_number] => 20150035498 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-02-05 [patent_title] => 'ACTIVE CONTROL PROCEDURES FOR THE CONNECTION OF VERY CAPACITIVE LOADS USING SSPCs' [patent_app_type] => utility [patent_app_number] => 13/996423 [patent_app_country] => US [patent_app_date] => 2011-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3614 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13996423 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9077640 [patent_doc_number] => 08555232 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-08 [patent_title] => 'Wire routing using virtual landing pads' [patent_app_type] => utility [patent_app_number] => 13/036308 [patent_app_country] => US [patent_app_date] => 2011-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 5416 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13036308 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13086013 [patent_doc_number] => 10063082 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-08-28 [patent_title] => Battery with cell balancing [patent_app_type] => utility [patent_app_number] => 13/641666 [patent_app_country] => US [patent_app_date] => 2011-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 3541 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 502 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13641666 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8162777 [patent_doc_number] => 20120102441 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-04-26 [patent_title] => 'MARKER LAYER TO FACILITATE MASK BUILD WITH INTERACTIVE LAYERS' [patent_app_type] => utility [patent_app_number] => 12/909034 [patent_app_country] => US [patent_app_date] => 2010-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4911 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0102/20120102441.pdf [firstpage_image] =>[orig_patent_app_number] => 12909034 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8142057 [patent_doc_number] => 20120095583 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-04-19 [patent_title] => 'ARCHITECTURE GUIDED OPTIMAL SYSTEM PRECISION DEFINITION ALGORITHM FOR CUSTOM INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/906804 [patent_app_country] => US [patent_app_date] => 2010-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4805 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0095/20120095583.pdf [firstpage_image] =>[orig_patent_app_number] => 12906804 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8959171 [patent_doc_number] => 08504965 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-08-06 [patent_title] => 'Method for non-shrinkable IP integration' [patent_app_type] => utility [patent_app_number] => 12/895264 [patent_app_country] => US [patent_app_date] => 2010-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3352 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12895264 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8935806 [patent_doc_number] => 08495528 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-07-23 [patent_title] => 'Method for generating a plurality of optimized wavefronts for a multiple exposure lithographic process' [patent_app_type] => utility [patent_app_number] => 12/890854 [patent_app_country] => US [patent_app_date] => 2010-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 9073 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 307 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12890854 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6020837 [patent_doc_number] => 20110225556 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-15 [patent_title] => 'PACKAGE SUBSTRATE DESIGN DEVICE, PACKAGE SUBSTRATE DESIGN METHOD, AND COMPUTER READABLE RECORDING MEDIUM FOR RECORDING PACKAGE SUBSTRATE DESIGN PROGRAM' [patent_app_type] => utility [patent_app_number] => 12/887314 [patent_app_country] => US [patent_app_date] => 2010-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4800 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0225/20110225556.pdf [firstpage_image] =>[orig_patent_app_number] => 12887314 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6117362 [patent_doc_number] => 20110191734 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-08-04 [patent_title] => 'DESIGNING APPARATUS, DESIGNING METHOD, AND COMPUTER READABLE MEDIUM' [patent_app_type] => utility [patent_app_number] => 12/887044 [patent_app_country] => US [patent_app_date] => 2010-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6139 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0191/20110191734.pdf [firstpage_image] =>[orig_patent_app_number] => 12887044 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5940331 [patent_doc_number] => 20110214099 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-01 [patent_title] => 'CIRCUIT DIAGRAM GENERATION SYSTEM AND METHOD' [patent_app_type] => utility [patent_app_number] => 12/884204 [patent_app_country] => US [patent_app_date] => 2010-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1634 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0214/20110214099.pdf [firstpage_image] =>[orig_patent_app_number] => 12884204 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6204201 [patent_doc_number] => 20110066987 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-17 [patent_title] => 'LAYOUT METHOD, LAYOUT DEVICE, AND NON-TRANSITORY COMPUTER READABLE MEDIUM STORING LAYOUT PROGRAM' [patent_app_type] => utility [patent_app_number] => 12/881724 [patent_app_country] => US [patent_app_date] => 2010-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5614 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0066/20110066987.pdf [firstpage_image] =>[orig_patent_app_number] => 12881724 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7819922 [patent_doc_number] => 20120066542 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-15 [patent_title] => 'Method for Node Addition and Removal of a Circuit' [patent_app_type] => utility [patent_app_number] => 12/880474 [patent_app_country] => US [patent_app_date] => 2010-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 9490 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0066/20120066542.pdf [firstpage_image] =>[orig_patent_app_number] => 12880474 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9116349 [patent_doc_number] => 08572541 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-29 [patent_title] => 'Method and system for adaptive physical design' [patent_app_type] => utility [patent_app_number] => 12/876138 [patent_app_country] => US [patent_app_date] => 2010-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 17 [patent_no_of_words] => 7567 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12876138 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9102871 [patent_doc_number] => 08566765 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-10-22 [patent_title] => 'In-hierarchy circuit analysis and modification' [patent_app_type] => utility [patent_app_number] => 12/871734 [patent_app_country] => US [patent_app_date] => 2010-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 3893 [patent_no_of_claims] => 51 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12871734 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7793142 [patent_doc_number] => 20120054698 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-01 [patent_title] => 'LOGIC MODIFICATION SYNTHESIS' [patent_app_type] => utility [patent_app_number] => 12/862838 [patent_app_country] => US [patent_app_date] => 2010-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5572 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0054/20120054698.pdf [firstpage_image] =>[orig_patent_app_number] => 12862838 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5991025 [patent_doc_number] => 20110099528 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-04-28 [patent_title] => 'HIGH-LEVEL SYNTHESIS APPARATUS, HIGH-LEVEL SYNTHESIS METHOD, AND COMPUTER READABLE MEDIUM' [patent_app_type] => utility [patent_app_number] => 12/861728 [patent_app_country] => US [patent_app_date] => 2010-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4642 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0099/20110099528.pdf [firstpage_image] =>[orig_patent_app_number] => 12861728 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6074258 [patent_doc_number] => 20110047518 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-02-24 [patent_title] => 'PATTERN DETERMINING METHOD' [patent_app_type] => utility [patent_app_number] => 12/860278 [patent_app_country] => US [patent_app_date] => 2010-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10857 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0047/20110047518.pdf [firstpage_image] =>[orig_patent_app_number] => 12860278 [rel_patent_id] =>[rel_patent_doc_number] =>)