
Eric D. Lee
Examiner (ID: 9865, Phone: (571)270-7098 , Office: P/2851 )
| Most Active Art Unit | 2851 |
| Art Unit(s) | 2825, 2851 |
| Total Applications | 764 |
| Issued Applications | 615 |
| Pending Applications | 44 |
| Abandoned Applications | 124 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 13086013
[patent_doc_number] => 10063082
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[patent_issue_date] => 2018-08-28
[patent_title] => Battery with cell balancing
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Array
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[patent_issue_date] => 2012-04-26
[patent_title] => 'MARKER LAYER TO FACILITATE MASK BUILD WITH INTERACTIVE LAYERS'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/909034 | Marker layer to facilitate mask build with interactive layers | Oct 20, 2010 | Issued |
Array
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[patent_doc_number] => 20120095583
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[patent_issue_date] => 2012-04-19
[patent_title] => 'ARCHITECTURE GUIDED OPTIMAL SYSTEM PRECISION DEFINITION ALGORITHM FOR CUSTOM INTEGRATED CIRCUIT'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/906804 | Architecture guided optimal system precision definition algorithm for custom integrated circuit | Oct 17, 2010 | Issued |
Array
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Array
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[patent_title] => 'Method for generating a plurality of optimized wavefronts for a multiple exposure lithographic process'
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Array
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[patent_title] => 'PACKAGE SUBSTRATE DESIGN DEVICE, PACKAGE SUBSTRATE DESIGN METHOD, AND COMPUTER READABLE RECORDING MEDIUM FOR RECORDING PACKAGE SUBSTRATE DESIGN PROGRAM'
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Array
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[id] => 5940331
[patent_doc_number] => 20110214099
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[patent_issue_date] => 2011-09-01
[patent_title] => 'CIRCUIT DIAGRAM GENERATION SYSTEM AND METHOD'
[patent_app_type] => utility
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Array
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Array
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[patent_issue_date] => 2012-03-15
[patent_title] => 'Method for Node Addition and Removal of a Circuit'
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Array
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Array
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Array
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Array
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Array
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