Search

Eric D. Lee

Examiner (ID: 9865, Phone: (571)270-7098 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2825, 2851
Total Applications
764
Issued Applications
615
Pending Applications
44
Abandoned Applications
124

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6449602 [patent_doc_number] => 20100169852 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-01 [patent_title] => 'SYSTEM AND METHOD FOR DETECTING ONE OR MORE WINDING PATHS FOR PATTERNS ON A RETICLE FOR THE MANUFACTURE OF SEMICONDUCTOR INTEGRATED CIRCUITS' [patent_app_type] => utility [patent_app_number] => 12/649278 [patent_app_country] => US [patent_app_date] => 2009-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7490 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0169/20100169852.pdf [firstpage_image] =>[orig_patent_app_number] => 12649278 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/649278
System and method for detecting one or more winding paths for patterns on a reticle for the manufacture of semiconductor integrated circuits Dec 28, 2009 Issued
Array ( [id] => 8427186 [patent_doc_number] => 20120249061 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-10-04 [patent_title] => 'ELECTROMOTIVE FORCE DEVICE' [patent_app_type] => utility [patent_app_number] => 13/516137 [patent_app_country] => US [patent_app_date] => 2009-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 8142 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13516137 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/516137
Electromotive force device Dec 23, 2009 Issued
Array ( [id] => 9404879 [patent_doc_number] => 08694944 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-04-08 [patent_title] => 'Predicting routability of integrated circuits' [patent_app_type] => utility [patent_app_number] => 12/643528 [patent_app_country] => US [patent_app_date] => 2009-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 7536 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12643528 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/643528
Predicting routability of integrated circuits Dec 20, 2009 Issued
Array ( [id] => 5974695 [patent_doc_number] => 20110153055 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-23 [patent_title] => 'WIDE-RANGE QUICK TUNABLE TRANSISTOR MODEL' [patent_app_type] => utility [patent_app_number] => 12/640398 [patent_app_country] => US [patent_app_date] => 2009-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4051 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0153/20110153055.pdf [firstpage_image] =>[orig_patent_app_number] => 12640398 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/640398
WIDE-RANGE QUICK TUNABLE TRANSISTOR MODEL Dec 16, 2009 Abandoned
Array ( [id] => 6088468 [patent_doc_number] => 20110145781 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-16 [patent_title] => 'Automated Framework for Programmable Logic Device Implementation of Integrated Circuit Design' [patent_app_type] => utility [patent_app_number] => 12/638178 [patent_app_country] => US [patent_app_date] => 2009-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 10599 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0145/20110145781.pdf [firstpage_image] =>[orig_patent_app_number] => 12638178 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/638178
Automated framework for programmable logic device implementation of integrated circuit design Dec 14, 2009 Issued
Array ( [id] => 6439883 [patent_doc_number] => 20100152875 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-17 [patent_title] => 'ESTIMATION APPARATUS AND ESTIMATION METHOD' [patent_app_type] => utility [patent_app_number] => 12/632258 [patent_app_country] => US [patent_app_date] => 2009-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 6485 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0152/20100152875.pdf [firstpage_image] =>[orig_patent_app_number] => 12632258 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/632258
ESTIMATION APPARATUS AND ESTIMATION METHOD Dec 6, 2009 Abandoned
Array ( [id] => 6472622 [patent_doc_number] => 20100191357 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-29 [patent_title] => 'PATTERN LAYOUT CREATION METHOD, PROGRAM PRODUCT, AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD' [patent_app_type] => utility [patent_app_number] => 12/630048 [patent_app_country] => US [patent_app_date] => 2009-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 11427 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0191/20100191357.pdf [firstpage_image] =>[orig_patent_app_number] => 12630048 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/630048
Pattern layout creation method, program product, and semiconductor device manufacturing method Dec 2, 2009 Issued
Array ( [id] => 6253707 [patent_doc_number] => 20100138803 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-03 [patent_title] => 'APPARATUS AND METHOD OF SUPPORTING DESIGN OF SEMICONDUCTOR INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/625968 [patent_app_country] => US [patent_app_date] => 2009-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7618 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0138/20100138803.pdf [firstpage_image] =>[orig_patent_app_number] => 12625968 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/625968
APPARATUS AND METHOD OF SUPPORTING DESIGN OF SEMICONDUCTOR INTEGRATED CIRCUIT Nov 24, 2009 Abandoned
Array ( [id] => 6241437 [patent_doc_number] => 20100269084 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-21 [patent_title] => 'Visibility and Transport Kernels for Variable Etch Bias Modeling of Optical Lithography' [patent_app_type] => utility [patent_app_number] => 12/625538 [patent_app_country] => US [patent_app_date] => 2009-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4432 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0269/20100269084.pdf [firstpage_image] =>[orig_patent_app_number] => 12625538 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/625538
Visibility and Transport Kernels for Variable Etch Bias Modeling of Optical Lithography Nov 23, 2009 Abandoned
Array ( [id] => 8604289 [patent_doc_number] => 20130009601 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-10 [patent_title] => 'BALANCING ELECTRICAL VOLTAGES OF ELECTRICAL ACCUMULATOR UNITS' [patent_app_type] => utility [patent_app_number] => 13/509157 [patent_app_country] => US [patent_app_date] => 2009-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3211 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13509157 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/509157
BALANCING ELECTRICAL VOLTAGES OF ELECTRICAL ACCUMULATOR UNITS Nov 18, 2009 Abandoned
Array ( [id] => 8810450 [patent_doc_number] => 08448117 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-05-21 [patent_title] => 'Adaptive mesh resolution in electric circuit simulation and analysis' [patent_app_type] => utility [patent_app_number] => 12/610948 [patent_app_country] => US [patent_app_date] => 2009-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 34 [patent_no_of_words] => 10699 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 270 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12610948 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/610948
Adaptive mesh resolution in electric circuit simulation and analysis Nov 1, 2009 Issued
Array ( [id] => 8849440 [patent_doc_number] => 08458640 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-06-04 [patent_title] => 'Routing using a dynamic grid' [patent_app_type] => utility [patent_app_number] => 12/608418 [patent_app_country] => US [patent_app_date] => 2009-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 20 [patent_no_of_words] => 11857 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12608418 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/608418
Routing using a dynamic grid Oct 28, 2009 Issued
Array ( [id] => 6100653 [patent_doc_number] => 20110004858 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-01-06 [patent_title] => 'METHOD FOR CONCURRENT MIGRATION AND DECOMPOSITION OF INTEGRATED CIRCUIT LAYOUT' [patent_app_type] => utility [patent_app_number] => 12/550484 [patent_app_country] => US [patent_app_date] => 2009-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5372 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0004/20110004858.pdf [firstpage_image] =>[orig_patent_app_number] => 12550484 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/550484
METHOD FOR CONCURRENT MIGRATION AND DECOMPOSITION OF INTEGRATED CIRCUIT LAYOUT Aug 30, 2009 Abandoned
Array ( [id] => 5376032 [patent_doc_number] => 20090313593 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-17 [patent_title] => 'Semiconductor integrated circuit design method and semiconductor integrated circuit design apparatus' [patent_app_type] => utility [patent_app_number] => 12/461585 [patent_app_country] => US [patent_app_date] => 2009-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 5151 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0313/20090313593.pdf [firstpage_image] =>[orig_patent_app_number] => 12461585 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/461585
Semiconductor integrated circuit design method and semiconductor integrated circuit design apparatus Aug 16, 2009 Abandoned
Array ( [id] => 6648812 [patent_doc_number] => 20100037191 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-02-11 [patent_title] => 'Method of generating reliability verification library for electromigration' [patent_app_type] => utility [patent_app_number] => 12/461067 [patent_app_country] => US [patent_app_date] => 2009-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 15837 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0037/20100037191.pdf [firstpage_image] =>[orig_patent_app_number] => 12461067 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/461067
Method of generating reliability verification library for electromigration Jul 29, 2009 Abandoned
Array ( [id] => 9029810 [patent_doc_number] => 08539408 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-09-17 [patent_title] => 'Method for thermal simulation' [patent_app_type] => utility [patent_app_number] => 12/462078 [patent_app_country] => US [patent_app_date] => 2009-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 13384 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12462078 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/462078
Method for thermal simulation Jul 28, 2009 Issued
Array ( [id] => 6648834 [patent_doc_number] => 20100037197 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-02-11 [patent_title] => 'Method and apparatus for integrated circuit design' [patent_app_type] => utility [patent_app_number] => 12/458279 [patent_app_country] => US [patent_app_date] => 2009-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4386 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0037/20100037197.pdf [firstpage_image] =>[orig_patent_app_number] => 12458279 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/458279
Method and apparatus for integrated circuit design Jul 6, 2009 Abandoned
Array ( [id] => 9077639 [patent_doc_number] => 08555231 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-08 [patent_title] => 'Automatic wiring device, automatic wiring method, and automatic wiring program' [patent_app_type] => utility [patent_app_number] => 12/458102 [patent_app_country] => US [patent_app_date] => 2009-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 16 [patent_no_of_words] => 4591 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12458102 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/458102
Automatic wiring device, automatic wiring method, and automatic wiring program Jun 29, 2009 Issued
Array ( [id] => 8273271 [patent_doc_number] => 08214787 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-07-03 [patent_title] => 'Cell uniquification' [patent_app_type] => utility [patent_app_number] => 12/479769 [patent_app_country] => US [patent_app_date] => 2009-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 81 [patent_no_of_words] => 13671 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12479769 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/479769
Cell uniquification Jun 5, 2009 Issued
Array ( [id] => 8170990 [patent_doc_number] => 08176448 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-05-08 [patent_title] => 'Method for N-variant integrated circuit (IC) design, and IC having N-variant circuits implemented therein' [patent_app_type] => utility [patent_app_number] => 12/479665 [patent_app_country] => US [patent_app_date] => 2009-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 12119 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/176/08176448.pdf [firstpage_image] =>[orig_patent_app_number] => 12479665 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/479665
Method for N-variant integrated circuit (IC) design, and IC having N-variant circuits implemented therein Jun 4, 2009 Issued
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