Eric D. Lee

Array ( [id] => 9102871 [patent_doc_number] => 08566765 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-10-22 [patent_title] => 'In-hierarchy circuit analysis and modification' [patent_app_type] => utility [patent_app_number] => 12/871734 [patent_app_country] => US [patent_app_date] => 2010-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 3893 [patent_no_of_claims] => 51 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12871734 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7793142 [patent_doc_number] => 20120054698 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-01 [patent_title] => 'LOGIC MODIFICATION SYNTHESIS' [patent_app_type] => utility [patent_app_number] => 12/862838 [patent_app_country] => US [patent_app_date] => 2010-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5572 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0054/20120054698.pdf [firstpage_image] =>[orig_patent_app_number] => 12862838 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5991025 [patent_doc_number] => 20110099528 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-04-28 [patent_title] => 'HIGH-LEVEL SYNTHESIS APPARATUS, HIGH-LEVEL SYNTHESIS METHOD, AND COMPUTER READABLE MEDIUM' [patent_app_type] => utility [patent_app_number] => 12/861728 [patent_app_country] => US [patent_app_date] => 2010-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4642 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0099/20110099528.pdf [firstpage_image] =>[orig_patent_app_number] => 12861728 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6074258 [patent_doc_number] => 20110047518 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-02-24 [patent_title] => 'PATTERN DETERMINING METHOD' [patent_app_type] => utility [patent_app_number] => 12/860278 [patent_app_country] => US [patent_app_date] => 2010-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10857 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0047/20110047518.pdf [firstpage_image] =>[orig_patent_app_number] => 12860278 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8285829 [patent_doc_number] => 08219946 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-07-10 [patent_title] => 'Method for clock gating circuits' [patent_app_type] => utility [patent_app_number] => 12/835638 [patent_app_country] => US [patent_app_date] => 2010-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 7387 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 285 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12835638 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8514180 [patent_doc_number] => 20120313588 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-12-13 [patent_title] => 'OCCUPANCY SENSOR WITH CONDITIONAL ENERGY TRANSFER FROM LOAD' [patent_app_type] => utility [patent_app_number] => 13/579888 [patent_app_country] => US [patent_app_date] => 2010-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6238 [patent_no_of_claims] => 60 [patent_no_of_ind_claims] => 26 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13579888 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6218087 [patent_doc_number] => 20110138343 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-09 [patent_title] => 'Pattern Transfer Modeling for Optical Lithographic Processes' [patent_app_type] => utility [patent_app_number] => 12/710353 [patent_app_country] => US [patent_app_date] => 2010-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8809 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0138/20110138343.pdf [firstpage_image] =>[orig_patent_app_number] => 12710353 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5957117 [patent_doc_number] => 20110035713 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-02-10 [patent_title] => 'CIRCUIT BOARD DESIGN SYSTEM AND METHOD' [patent_app_type] => utility [patent_app_number] => 12/650758 [patent_app_country] => US [patent_app_date] => 2009-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1323 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0035/20110035713.pdf [firstpage_image] =>[orig_patent_app_number] => 12650758 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9029818 [patent_doc_number] => 08539416 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-09-17 [patent_title] => 'Methods, systems, and articles of manufacture for creating a hierarchical output for an operation in an electronic design' [patent_app_type] => utility [patent_app_number] => 12/649658 [patent_app_country] => US [patent_app_date] => 2009-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 16 [patent_no_of_words] => 15357 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12649658 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6449602 [patent_doc_number] => 20100169852 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-01 [patent_title] => 'SYSTEM AND METHOD FOR DETECTING ONE OR MORE WINDING PATHS FOR PATTERNS ON A RETICLE FOR THE MANUFACTURE OF SEMICONDUCTOR INTEGRATED CIRCUITS' [patent_app_type] => utility [patent_app_number] => 12/649278 [patent_app_country] => US [patent_app_date] => 2009-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7490 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0169/20100169852.pdf [firstpage_image] =>[orig_patent_app_number] => 12649278 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8427186 [patent_doc_number] => 20120249061 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-10-04 [patent_title] => 'ELECTROMOTIVE FORCE DEVICE' [patent_app_type] => utility [patent_app_number] => 13/516137 [patent_app_country] => US [patent_app_date] => 2009-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 8142 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13516137 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9404879 [patent_doc_number] => 08694944 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-04-08 [patent_title] => 'Predicting routability of integrated circuits' [patent_app_type] => utility [patent_app_number] => 12/643528 [patent_app_country] => US [patent_app_date] => 2009-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 7536 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12643528 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5974695 [patent_doc_number] => 20110153055 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-23 [patent_title] => 'WIDE-RANGE QUICK TUNABLE TRANSISTOR MODEL' [patent_app_type] => utility [patent_app_number] => 12/640398 [patent_app_country] => US [patent_app_date] => 2009-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4051 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0153/20110153055.pdf [firstpage_image] =>[orig_patent_app_number] => 12640398 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6088468 [patent_doc_number] => 20110145781 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-16 [patent_title] => 'Automated Framework for Programmable Logic Device Implementation of Integrated Circuit Design' [patent_app_type] => utility [patent_app_number] => 12/638178 [patent_app_country] => US [patent_app_date] => 2009-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 10599 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0145/20110145781.pdf [firstpage_image] =>[orig_patent_app_number] => 12638178 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6439883 [patent_doc_number] => 20100152875 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-17 [patent_title] => 'ESTIMATION APPARATUS AND ESTIMATION METHOD' [patent_app_type] => utility [patent_app_number] => 12/632258 [patent_app_country] => US [patent_app_date] => 2009-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 6485 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0152/20100152875.pdf [firstpage_image] =>[orig_patent_app_number] => 12632258 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6472622 [patent_doc_number] => 20100191357 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-29 [patent_title] => 'PATTERN LAYOUT CREATION METHOD, PROGRAM PRODUCT, AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD' [patent_app_type] => utility [patent_app_number] => 12/630048 [patent_app_country] => US [patent_app_date] => 2009-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 11427 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0191/20100191357.pdf [firstpage_image] =>[orig_patent_app_number] => 12630048 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6253707 [patent_doc_number] => 20100138803 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-03 [patent_title] => 'APPARATUS AND METHOD OF SUPPORTING DESIGN OF SEMICONDUCTOR INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/625968 [patent_app_country] => US [patent_app_date] => 2009-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7618 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0138/20100138803.pdf [firstpage_image] =>[orig_patent_app_number] => 12625968 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6241437 [patent_doc_number] => 20100269084 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-21 [patent_title] => 'Visibility and Transport Kernels for Variable Etch Bias Modeling of Optical Lithography' [patent_app_type] => utility [patent_app_number] => 12/625538 [patent_app_country] => US [patent_app_date] => 2009-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4432 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0269/20100269084.pdf [firstpage_image] =>[orig_patent_app_number] => 12625538 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8604289 [patent_doc_number] => 20130009601 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-10 [patent_title] => 'BALANCING ELECTRICAL VOLTAGES OF ELECTRICAL ACCUMULATOR UNITS' [patent_app_type] => utility [patent_app_number] => 13/509157 [patent_app_country] => US [patent_app_date] => 2009-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3211 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13509157 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8810450 [patent_doc_number] => 08448117 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-05-21 [patent_title] => 'Adaptive mesh resolution in electric circuit simulation and analysis' [patent_app_type] => utility [patent_app_number] => 12/610948 [patent_app_country] => US [patent_app_date] => 2009-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 34 [patent_no_of_words] => 10699 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 270 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12610948 [rel_patent_id] =>[rel_patent_doc_number] =>)