Search

Eric D. Lee

Examiner (ID: 1963, Phone: (571)270-7098 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2851, 2825
Total Applications
773
Issued Applications
618
Pending Applications
46
Abandoned Applications
125

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8849440 [patent_doc_number] => 08458640 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-06-04 [patent_title] => 'Routing using a dynamic grid' [patent_app_type] => utility [patent_app_number] => 12/608418 [patent_app_country] => US [patent_app_date] => 2009-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 20 [patent_no_of_words] => 11857 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12608418 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/608418
Routing using a dynamic grid Oct 28, 2009 Issued
Array ( [id] => 6100653 [patent_doc_number] => 20110004858 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-01-06 [patent_title] => 'METHOD FOR CONCURRENT MIGRATION AND DECOMPOSITION OF INTEGRATED CIRCUIT LAYOUT' [patent_app_type] => utility [patent_app_number] => 12/550484 [patent_app_country] => US [patent_app_date] => 2009-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5372 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0004/20110004858.pdf [firstpage_image] =>[orig_patent_app_number] => 12550484 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/550484
METHOD FOR CONCURRENT MIGRATION AND DECOMPOSITION OF INTEGRATED CIRCUIT LAYOUT Aug 30, 2009 Abandoned
Array ( [id] => 5376032 [patent_doc_number] => 20090313593 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-17 [patent_title] => 'Semiconductor integrated circuit design method and semiconductor integrated circuit design apparatus' [patent_app_type] => utility [patent_app_number] => 12/461585 [patent_app_country] => US [patent_app_date] => 2009-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 5151 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0313/20090313593.pdf [firstpage_image] =>[orig_patent_app_number] => 12461585 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/461585
Semiconductor integrated circuit design method and semiconductor integrated circuit design apparatus Aug 16, 2009 Abandoned
Array ( [id] => 6648812 [patent_doc_number] => 20100037191 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-02-11 [patent_title] => 'Method of generating reliability verification library for electromigration' [patent_app_type] => utility [patent_app_number] => 12/461067 [patent_app_country] => US [patent_app_date] => 2009-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 15837 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0037/20100037191.pdf [firstpage_image] =>[orig_patent_app_number] => 12461067 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/461067
Method of generating reliability verification library for electromigration Jul 29, 2009 Abandoned
Array ( [id] => 9029810 [patent_doc_number] => 08539408 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-09-17 [patent_title] => 'Method for thermal simulation' [patent_app_type] => utility [patent_app_number] => 12/462078 [patent_app_country] => US [patent_app_date] => 2009-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 13384 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12462078 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/462078
Method for thermal simulation Jul 28, 2009 Issued
Array ( [id] => 6648834 [patent_doc_number] => 20100037197 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-02-11 [patent_title] => 'Method and apparatus for integrated circuit design' [patent_app_type] => utility [patent_app_number] => 12/458279 [patent_app_country] => US [patent_app_date] => 2009-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4386 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0037/20100037197.pdf [firstpage_image] =>[orig_patent_app_number] => 12458279 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/458279
Method and apparatus for integrated circuit design Jul 6, 2009 Abandoned
Array ( [id] => 9077639 [patent_doc_number] => 08555231 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-08 [patent_title] => 'Automatic wiring device, automatic wiring method, and automatic wiring program' [patent_app_type] => utility [patent_app_number] => 12/458102 [patent_app_country] => US [patent_app_date] => 2009-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 16 [patent_no_of_words] => 4591 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12458102 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/458102
Automatic wiring device, automatic wiring method, and automatic wiring program Jun 29, 2009 Issued
Array ( [id] => 8273271 [patent_doc_number] => 08214787 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-07-03 [patent_title] => 'Cell uniquification' [patent_app_type] => utility [patent_app_number] => 12/479769 [patent_app_country] => US [patent_app_date] => 2009-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 81 [patent_no_of_words] => 13671 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12479769 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/479769
Cell uniquification Jun 5, 2009 Issued
Array ( [id] => 8170990 [patent_doc_number] => 08176448 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-05-08 [patent_title] => 'Method for N-variant integrated circuit (IC) design, and IC having N-variant circuits implemented therein' [patent_app_type] => utility [patent_app_number] => 12/479665 [patent_app_country] => US [patent_app_date] => 2009-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 12119 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/176/08176448.pdf [firstpage_image] =>[orig_patent_app_number] => 12479665 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/479665
Method for N-variant integrated circuit (IC) design, and IC having N-variant circuits implemented therein Jun 4, 2009 Issued
Array ( [id] => 6512079 [patent_doc_number] => 20100011324 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-01-14 [patent_title] => 'Structured Placement For Bit Slices' [patent_app_type] => utility [patent_app_number] => 12/479681 [patent_app_country] => US [patent_app_date] => 2009-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2683 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0011/20100011324.pdf [firstpage_image] =>[orig_patent_app_number] => 12479681 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/479681
Structured placement for bit slices Jun 4, 2009 Issued
Array ( [id] => 5467783 [patent_doc_number] => 20090327983 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-31 [patent_title] => 'Predictive Modeling of Interconnect Modules for Advanced On-Chip Interconnect Technology' [patent_app_type] => utility [patent_app_number] => 12/474297 [patent_app_country] => US [patent_app_date] => 2009-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 12235 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0327/20090327983.pdf [firstpage_image] =>[orig_patent_app_number] => 12474297 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/474297
Predictive modeling of interconnect modules for advanced on-chip interconnect technology May 28, 2009 Issued
Array ( [id] => 7530118 [patent_doc_number] => 08046724 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-10-25 [patent_title] => 'Method of timing criticality calculation for statistical timing optimization of VLSI circuit' [patent_app_type] => utility [patent_app_number] => 12/474547 [patent_app_country] => US [patent_app_date] => 2009-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 5768 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/046/08046724.pdf [firstpage_image] =>[orig_patent_app_number] => 12474547 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/474547
Method of timing criticality calculation for statistical timing optimization of VLSI circuit May 28, 2009 Issued
Array ( [id] => 5490441 [patent_doc_number] => 20090291512 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-11-26 [patent_title] => 'SEMICONDUCTOR DEVICE PATTERN VERIFICATION METHOD, SEMICONDUCTOR DEVICE PATTERN VERIFICATION PROGRAM, AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD' [patent_app_type] => utility [patent_app_number] => 12/470289 [patent_app_country] => US [patent_app_date] => 2009-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 20306 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0291/20090291512.pdf [firstpage_image] =>[orig_patent_app_number] => 12470289 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/470289
SEMICONDUCTOR DEVICE PATTERN VERIFICATION METHOD, SEMICONDUCTOR DEVICE PATTERN VERIFICATION PROGRAM, AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD May 20, 2009 Abandoned
Array ( [id] => 8752249 [patent_doc_number] => 08418093 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-04-09 [patent_title] => 'Method and system for design simplification through implication-based analysis' [patent_app_type] => utility [patent_app_number] => 12/467097 [patent_app_country] => US [patent_app_date] => 2009-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7012 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12467097 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/467097
Method and system for design simplification through implication-based analysis May 14, 2009 Issued
Array ( [id] => 5491962 [patent_doc_number] => 20090293033 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-11-26 [patent_title] => 'System and method for layout design of integrated circuit' [patent_app_type] => utility [patent_app_number] => 12/453559 [patent_app_country] => US [patent_app_date] => 2009-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5266 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0293/20090293033.pdf [firstpage_image] =>[orig_patent_app_number] => 12453559 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/453559
System and method for layout design of integrated circuit May 13, 2009 Abandoned
Array ( [id] => 5554066 [patent_doc_number] => 20090288052 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-11-19 [patent_title] => 'METHOD AND APPARATUS FOR ANALYZING CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/464120 [patent_app_country] => US [patent_app_date] => 2009-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5655 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0288/20090288052.pdf [firstpage_image] =>[orig_patent_app_number] => 12464120 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/464120
METHOD AND APPARATUS FOR ANALYZING CIRCUIT May 11, 2009 Abandoned
Array ( [id] => 8655579 [patent_doc_number] => 08375347 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-02-12 [patent_title] => 'Driven metal critical dimension (CD) biasing' [patent_app_type] => utility [patent_app_number] => 12/464578 [patent_app_country] => US [patent_app_date] => 2009-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4571 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12464578 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/464578
Driven metal critical dimension (CD) biasing May 11, 2009 Issued
Array ( [id] => 6537271 [patent_doc_number] => 20100287519 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-11-11 [patent_title] => 'METHOD AND SYSTEM FOR CONSTRUCTING A CUSTOMIZED LAYOUT FIGURE GROUP' [patent_app_type] => utility [patent_app_number] => 12/463689 [patent_app_country] => US [patent_app_date] => 2009-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 3280 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0287/20100287519.pdf [firstpage_image] =>[orig_patent_app_number] => 12463689 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/463689
METHOD AND SYSTEM FOR CONSTRUCTING A CUSTOMIZED LAYOUT FIGURE GROUP May 10, 2009 Abandoned
Array ( [id] => 8741311 [patent_doc_number] => 08413098 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-04-02 [patent_title] => 'T-connections, methodology for designing T-connections, and compact modeling of T-connections' [patent_app_type] => utility [patent_app_number] => 12/431887 [patent_app_country] => US [patent_app_date] => 2009-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 22 [patent_no_of_words] => 6937 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12431887 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/431887
T-connections, methodology for designing T-connections, and compact modeling of T-connections Apr 28, 2009 Issued
Array ( [id] => 5317780 [patent_doc_number] => 20090282378 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-11-12 [patent_title] => 'Semiconductor device design support apparatus and semiconductor device design support method' [patent_app_type] => utility [patent_app_number] => 12/385879 [patent_app_country] => US [patent_app_date] => 2009-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3468 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0282/20090282378.pdf [firstpage_image] =>[orig_patent_app_number] => 12385879 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/385879
Semiconductor device design support apparatus and semiconductor device design support method Apr 21, 2009 Issued
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