Eric D. Lee

Array ( [id] => 6512079 [patent_doc_number] => 20100011324 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-01-14 [patent_title] => 'Structured Placement For Bit Slices' [patent_app_type] => utility [patent_app_number] => 12/479681 [patent_app_country] => US [patent_app_date] => 2009-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2683 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0011/20100011324.pdf [firstpage_image] =>[orig_patent_app_number] => 12479681 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7530118 [patent_doc_number] => 08046724 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-10-25 [patent_title] => 'Method of timing criticality calculation for statistical timing optimization of VLSI circuit' [patent_app_type] => utility [patent_app_number] => 12/474547 [patent_app_country] => US [patent_app_date] => 2009-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 5768 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/046/08046724.pdf [firstpage_image] =>[orig_patent_app_number] => 12474547 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5467783 [patent_doc_number] => 20090327983 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-31 [patent_title] => 'Predictive Modeling of Interconnect Modules for Advanced On-Chip Interconnect Technology' [patent_app_type] => utility [patent_app_number] => 12/474297 [patent_app_country] => US [patent_app_date] => 2009-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 12235 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0327/20090327983.pdf [firstpage_image] =>[orig_patent_app_number] => 12474297 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5490441 [patent_doc_number] => 20090291512 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-11-26 [patent_title] => 'SEMICONDUCTOR DEVICE PATTERN VERIFICATION METHOD, SEMICONDUCTOR DEVICE PATTERN VERIFICATION PROGRAM, AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD' [patent_app_type] => utility [patent_app_number] => 12/470289 [patent_app_country] => US [patent_app_date] => 2009-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 20306 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0291/20090291512.pdf [firstpage_image] =>[orig_patent_app_number] => 12470289 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8752249 [patent_doc_number] => 08418093 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-04-09 [patent_title] => 'Method and system for design simplification through implication-based analysis' [patent_app_type] => utility [patent_app_number] => 12/467097 [patent_app_country] => US [patent_app_date] => 2009-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7012 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12467097 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5491962 [patent_doc_number] => 20090293033 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-11-26 [patent_title] => 'System and method for layout design of integrated circuit' [patent_app_type] => utility [patent_app_number] => 12/453559 [patent_app_country] => US [patent_app_date] => 2009-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5266 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0293/20090293033.pdf [firstpage_image] =>[orig_patent_app_number] => 12453559 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8655579 [patent_doc_number] => 08375347 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-02-12 [patent_title] => 'Driven metal critical dimension (CD) biasing' [patent_app_type] => utility [patent_app_number] => 12/464578 [patent_app_country] => US [patent_app_date] => 2009-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4571 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12464578 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5554066 [patent_doc_number] => 20090288052 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-11-19 [patent_title] => 'METHOD AND APPARATUS FOR ANALYZING CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/464120 [patent_app_country] => US [patent_app_date] => 2009-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5655 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0288/20090288052.pdf [firstpage_image] =>[orig_patent_app_number] => 12464120 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6537271 [patent_doc_number] => 20100287519 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-11-11 [patent_title] => 'METHOD AND SYSTEM FOR CONSTRUCTING A CUSTOMIZED LAYOUT FIGURE GROUP' [patent_app_type] => utility [patent_app_number] => 12/463689 [patent_app_country] => US [patent_app_date] => 2009-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 3280 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0287/20100287519.pdf [firstpage_image] =>[orig_patent_app_number] => 12463689 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8741311 [patent_doc_number] => 08413098 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-04-02 [patent_title] => 'T-connections, methodology for designing T-connections, and compact modeling of T-connections' [patent_app_type] => utility [patent_app_number] => 12/431887 [patent_app_country] => US [patent_app_date] => 2009-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 22 [patent_no_of_words] => 6937 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12431887 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8873098 [patent_doc_number] => 08468487 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-06-18 [patent_title] => 'Method and apparatus for implementing cross-talk based booster wires in a system on a field programmable gate array' [patent_app_type] => utility [patent_app_number] => 12/386739 [patent_app_country] => US [patent_app_date] => 2009-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5893 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12386739 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5317780 [patent_doc_number] => 20090282378 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-11-12 [patent_title] => 'Semiconductor device design support apparatus and semiconductor device design support method' [patent_app_type] => utility [patent_app_number] => 12/385879 [patent_app_country] => US [patent_app_date] => 2009-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3468 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0282/20090282378.pdf [firstpage_image] =>[orig_patent_app_number] => 12385879 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6241425 [patent_doc_number] => 20100269078 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-21 [patent_title] => 'AUTOMATIC APPROXIMATION OF ASSUMPTIONS FOR FORMAL PROPERTY VERIFICATION' [patent_app_type] => utility [patent_app_number] => 12/425597 [patent_app_country] => US [patent_app_date] => 2009-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7684 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0269/20100269078.pdf [firstpage_image] =>[orig_patent_app_number] => 12425597 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6241419 [patent_doc_number] => 20100269074 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-21 [patent_title] => 'Predictive Power Management Semiconductor Design Tool and Methods for Using Such' [patent_app_type] => utility [patent_app_number] => 12/425547 [patent_app_country] => US [patent_app_date] => 2009-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 17239 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0269/20100269074.pdf [firstpage_image] =>[orig_patent_app_number] => 12425547 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6240920 [patent_doc_number] => 20100268917 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-21 [patent_title] => 'Systems and Methods for Ramped Power State Control in a Semiconductor Device' [patent_app_type] => utility [patent_app_number] => 12/425507 [patent_app_country] => US [patent_app_date] => 2009-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 17237 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0268/20100268917.pdf [firstpage_image] =>[orig_patent_app_number] => 12425507 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6535236 [patent_doc_number] => 20100262940 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-14 [patent_title] => 'Accurate Approximation of Resistance in a Wire with Irregular Biasing and Determination of Interconnect Capacitances in VLSI Layouts in the Presence of Catastrophic Optical Proximity Correction' [patent_app_type] => utility [patent_app_number] => 12/423387 [patent_app_country] => US [patent_app_date] => 2009-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6676 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0262/20100262940.pdf [firstpage_image] =>[orig_patent_app_number] => 12423387 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4632003 [patent_doc_number] => 08010913 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-08-30 [patent_title] => 'Model-based assist feature placement using inverse imaging approach' [patent_app_type] => utility [patent_app_number] => 12/386199 [patent_app_country] => US [patent_app_date] => 2009-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 6518 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/010/08010913.pdf [firstpage_image] =>[orig_patent_app_number] => 12386199 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9486687 [patent_doc_number] => 08732651 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-05-20 [patent_title] => 'Logical design flow with structural compatability verification' [patent_app_type] => utility [patent_app_number] => 12/422959 [patent_app_country] => US [patent_app_date] => 2009-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 24 [patent_no_of_words] => 13360 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12422959 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8273253 [patent_doc_number] => 08214777 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-07-03 [patent_title] => 'On-chip leakage current modeling and measurement circuit' [patent_app_type] => utility [patent_app_number] => 12/419377 [patent_app_country] => US [patent_app_date] => 2009-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 4111 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 381 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12419377 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9486676 [patent_doc_number] => 08732639 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-05-20 [patent_title] => 'Method and apparatus for protecting, optimizing, and reporting synchronizers' [patent_app_type] => utility [patent_app_number] => 12/384377 [patent_app_country] => US [patent_app_date] => 2009-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7933 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12384377 [rel_patent_id] =>[rel_patent_doc_number] =>)