Search

Eric D. Lee

Examiner (ID: 9865, Phone: (571)270-7098 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2825, 2851
Total Applications
764
Issued Applications
615
Pending Applications
44
Abandoned Applications
124

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6505439 [patent_doc_number] => 20100216061 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-26 [patent_title] => 'Inverse Lithography For High Transmission Attenuated Phase Shift Mask Design And Creation' [patent_app_type] => utility [patent_app_number] => 12/416037 [patent_app_country] => US [patent_app_date] => 2009-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6331 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0216/20100216061.pdf [firstpage_image] =>[orig_patent_app_number] => 12416037 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/416037
Inverse Lithography For High Transmission Attenuated Phase Shift Mask Design And Creation Mar 30, 2009 Abandoned
Array ( [id] => 8678849 [patent_doc_number] => 08386987 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-02-26 [patent_title] => 'Method and system for implementing and analyzing power switch configurations' [patent_app_type] => utility [patent_app_number] => 12/414377 [patent_app_country] => US [patent_app_date] => 2009-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4745 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12414377 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/414377
Method and system for implementing and analyzing power switch configurations Mar 29, 2009 Issued
Array ( [id] => 5470227 [patent_doc_number] => 20090243393 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-10-01 [patent_title] => 'SEMICONDUCTOR DEVICE, DESIGNING METHOD AND DESIGNING APPARATUS OF THE SAME' [patent_app_type] => utility [patent_app_number] => 12/411607 [patent_app_country] => US [patent_app_date] => 2009-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7454 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0243/20090243393.pdf [firstpage_image] =>[orig_patent_app_number] => 12411607 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/411607
SEMICONDUCTOR DEVICE, DESIGNING METHOD AND DESIGNING APPARATUS OF THE SAME Mar 25, 2009 Abandoned
Array ( [id] => 8985289 [patent_doc_number] => 08516419 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-08-20 [patent_title] => 'Verification device of semiconductor integrated circuit, verification method of semiconductor integrated circuit, and computer readable medium storing verification program of semiconductor integrated circuit' [patent_app_type] => utility [patent_app_number] => 12/405400 [patent_app_country] => US [patent_app_date] => 2009-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 3630 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12405400 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/405400
Verification device of semiconductor integrated circuit, verification method of semiconductor integrated circuit, and computer readable medium storing verification program of semiconductor integrated circuit Mar 16, 2009 Issued
Array ( [id] => 8472871 [patent_doc_number] => 08302064 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-10-30 [patent_title] => 'Method of product performance improvement by selective feature sizing of semiconductor devices' [patent_app_type] => utility [patent_app_number] => 12/401450 [patent_app_country] => US [patent_app_date] => 2009-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 6384 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 239 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12401450 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/401450
Method of product performance improvement by selective feature sizing of semiconductor devices Mar 9, 2009 Issued
Array ( [id] => 8366770 [patent_doc_number] => 08255848 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-08-28 [patent_title] => 'Logic design verification techniques for liveness checking with retiming' [patent_app_type] => utility [patent_app_number] => 12/394560 [patent_app_country] => US [patent_app_date] => 2009-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 9915 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 260 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12394560 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/394560
Logic design verification techniques for liveness checking with retiming Feb 26, 2009 Issued
Array ( [id] => 5540979 [patent_doc_number] => 20090222784 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-09-03 [patent_title] => 'Design method estimating signal delay time with netlist in light of terminal line in macro, and program' [patent_app_type] => utility [patent_app_number] => 12/379350 [patent_app_country] => US [patent_app_date] => 2009-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7083 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0222/20090222784.pdf [firstpage_image] =>[orig_patent_app_number] => 12379350 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/379350
Design method estimating signal delay time with netlist in light of terminal line in macro, and program Feb 18, 2009 Abandoned
Array ( [id] => 8536239 [patent_doc_number] => 08312405 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-11-13 [patent_title] => 'Method of placing input/output blocks on an integrated circuit device' [patent_app_type] => utility [patent_app_number] => 12/356349 [patent_app_country] => US [patent_app_date] => 2009-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 8718 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12356349 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/356349
Method of placing input/output blocks on an integrated circuit device Jan 19, 2009 Issued
Array ( [id] => 5355080 [patent_doc_number] => 20090186424 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-23 [patent_title] => 'PATTERN GENERATION METHOD, COMPUTER-READABLE RECORDING MEDIUM, AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD' [patent_app_type] => utility [patent_app_number] => 12/354119 [patent_app_country] => US [patent_app_date] => 2009-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5355 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0186/20090186424.pdf [firstpage_image] =>[orig_patent_app_number] => 12354119 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/354119
Pattern generation method, computer-readable recording medium, and semiconductor device manufacturing method Jan 14, 2009 Issued
Array ( [id] => 6647880 [patent_doc_number] => 20100175038 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-08 [patent_title] => 'Techniques for Implementing an Engineering Change Order in an Integrated Circuit Design' [patent_app_type] => utility [patent_app_number] => 12/349289 [patent_app_country] => US [patent_app_date] => 2009-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3888 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0175/20100175038.pdf [firstpage_image] =>[orig_patent_app_number] => 12349289 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/349289
Techniques for Implementing an Engineering Change Order in an Integrated Circuit Design Jan 5, 2009 Abandoned
Array ( [id] => 8574904 [patent_doc_number] => 08341567 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-12-25 [patent_title] => 'Boolean satisfiability based verification of analog circuits' [patent_app_type] => utility [patent_app_number] => 12/345449 [patent_app_country] => US [patent_app_date] => 2008-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 26 [patent_no_of_words] => 11241 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 293 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12345449 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/345449
Boolean satisfiability based verification of analog circuits Dec 28, 2008 Issued
Array ( [id] => 4637057 [patent_doc_number] => 08015522 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-09-06 [patent_title] => 'System for implementing post-silicon IC design changes' [patent_app_type] => utility [patent_app_number] => 12/345399 [patent_app_country] => US [patent_app_date] => 2008-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 30 [patent_no_of_words] => 9774 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 280 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/015/08015522.pdf [firstpage_image] =>[orig_patent_app_number] => 12345399 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/345399
System for implementing post-silicon IC design changes Dec 28, 2008 Issued
Array ( [id] => 5438034 [patent_doc_number] => 20090172621 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-02 [patent_title] => 'SYSTEM AND METHOD FOR SYSTEM-ON-CHIP (SOC) PERFORMANCE ANALYSIS' [patent_app_type] => utility [patent_app_number] => 12/344879 [patent_app_country] => US [patent_app_date] => 2008-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6819 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0172/20090172621.pdf [firstpage_image] =>[orig_patent_app_number] => 12344879 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/344879
SYSTEM AND METHOD FOR SYSTEM-ON-CHIP (SOC) PERFORMANCE ANALYSIS Dec 28, 2008 Abandoned
Array ( [id] => 8183350 [patent_doc_number] => 08181139 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-05-15 [patent_title] => 'Multi-priority placement for configuring programmable logic devices' [patent_app_type] => utility [patent_app_number] => 12/341929 [patent_app_country] => US [patent_app_date] => 2008-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3592 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/181/08181139.pdf [firstpage_image] =>[orig_patent_app_number] => 12341929 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/341929
Multi-priority placement for configuring programmable logic devices Dec 21, 2008 Issued
Array ( [id] => 8378408 [patent_doc_number] => 08261215 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-09-04 [patent_title] => 'Method and system for performing cell modeling and selection' [patent_app_type] => utility [patent_app_number] => 12/342039 [patent_app_country] => US [patent_app_date] => 2008-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6189 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12342039 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/342039
Method and system for performing cell modeling and selection Dec 21, 2008 Issued
Array ( [id] => 5437897 [patent_doc_number] => 20090172484 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-02 [patent_title] => ' Method for Implementing a Serialization Construct Within an Environment of Parallel Data Flow Graphs' [patent_app_type] => utility [patent_app_number] => 12/330890 [patent_app_country] => US [patent_app_date] => 2008-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2826 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0172/20090172484.pdf [firstpage_image] =>[orig_patent_app_number] => 12330890 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/330890
Implementing a serialization construct within an environment of parallel data flow graphs Dec 8, 2008 Issued
Array ( [id] => 4642091 [patent_doc_number] => 08020127 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-09-13 [patent_title] => 'Clock frequency exploration for circuit designs having multiple clock domains' [patent_app_type] => utility [patent_app_number] => 12/275658 [patent_app_country] => US [patent_app_date] => 2008-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 6591 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/020/08020127.pdf [firstpage_image] =>[orig_patent_app_number] => 12275658 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/275658
Clock frequency exploration for circuit designs having multiple clock domains Nov 20, 2008 Issued
Array ( [id] => 5332897 [patent_doc_number] => 20090113374 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-30 [patent_title] => 'Method for designing semiconductor device layout and layout design supporting apparatus' [patent_app_type] => utility [patent_app_number] => 12/289198 [patent_app_country] => US [patent_app_date] => 2008-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6395 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0113/20090113374.pdf [firstpage_image] =>[orig_patent_app_number] => 12289198 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/289198
Method for designing semiconductor device layout and layout design supporting apparatus Oct 21, 2008 Abandoned
Array ( [id] => 6630228 [patent_doc_number] => 20100100856 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-22 [patent_title] => 'Automated optimization of an integrated circuit layout using cost functions associated with circuit performance characteristics' [patent_app_type] => utility [patent_app_number] => 12/288268 [patent_app_country] => US [patent_app_date] => 2008-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5667 [patent_no_of_claims] => 47 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0100/20100100856.pdf [firstpage_image] =>[orig_patent_app_number] => 12288268 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/288268
Automated optimization of an integrated circuit layout using cost functions associated with circuit performance characteristics Oct 16, 2008 Abandoned
Array ( [id] => 8424773 [patent_doc_number] => 08281271 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-10-02 [patent_title] => 'Method and apparatus for performing lutmask based delay modeling' [patent_app_type] => utility [patent_app_number] => 12/287828 [patent_app_country] => US [patent_app_date] => 2008-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6453 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12287828 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/287828
Method and apparatus for performing lutmask based delay modeling Oct 13, 2008 Issued
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