Eric D. Lee

Array ( [id] => 7553292 [patent_doc_number] => 08065634 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-11-22 [patent_title] => 'System and method for analyzing a nanotube logic circuit' [patent_app_type] => utility [patent_app_number] => 12/240409 [patent_app_country] => US [patent_app_date] => 2008-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 29 [patent_no_of_words] => 7214 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/065/08065634.pdf [firstpage_image] =>[orig_patent_app_number] => 12240409 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8959166 [patent_doc_number] => 08504960 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-08-06 [patent_title] => 'Method and system for high speed and low memory footprint static timing analysis' [patent_app_type] => utility [patent_app_number] => 12/451308 [patent_app_country] => US [patent_app_date] => 2008-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2593 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12451308 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6332873 [patent_doc_number] => 20100115488 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-05-06 [patent_title] => 'CIRCUIT DESIGN DEVICE, CIRCUIT DESIGN METHOD, AND CIRCUIT DESIGN PROGRAM' [patent_app_type] => utility [patent_app_number] => 12/595828 [patent_app_country] => US [patent_app_date] => 2008-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8688 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0115/20100115488.pdf [firstpage_image] =>[orig_patent_app_number] => 12595828 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5535434 [patent_doc_number] => 20090235222 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-09-17 [patent_title] => 'CREATING A STANDARD CELL CIRCUIT DESIGN FROM A PROGRAMMABLE LOGIC DEVICE CIRCUIT DESIGN' [patent_app_type] => utility [patent_app_number] => 12/049676 [patent_app_country] => US [patent_app_date] => 2008-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 6071 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0235/20090235222.pdf [firstpage_image] =>[orig_patent_app_number] => 12049676 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10834861 [patent_doc_number] => 08863056 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-10-14 [patent_title] => 'Integrated design-for-manufacturing platform' [patent_app_type] => utility [patent_app_number] => 11/844186 [patent_app_country] => US [patent_app_date] => 2007-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3369 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11844186 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6652443 [patent_doc_number] => 20100229140 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-09 [patent_title] => 'METHOD AND SYSTEM FOR ADAPTING A CIRCUIT LAYOUT TO A PREDEFINED GRID' [patent_app_type] => utility [patent_app_number] => 12/376427 [patent_app_country] => US [patent_app_date] => 2007-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9535 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0229/20100229140.pdf [firstpage_image] =>[orig_patent_app_number] => 12376427 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6449678 [patent_doc_number] => 20100169856 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-01 [patent_title] => 'TRANSPARENT TEST METHOD AND SCAN FLIP-FLOP' [patent_app_type] => utility [patent_app_number] => 12/303938 [patent_app_country] => US [patent_app_date] => 2007-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 8086 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0169/20100169856.pdf [firstpage_image] =>[orig_patent_app_number] => 12303938 [rel_patent_id] =>[rel_patent_doc_number] =>)