
Eric D. Lee
Examiner (ID: 17546)
| Most Active Art Unit | 2851 |
| Art Unit(s) | 2851, 2825 |
| Total Applications | 769 |
| Issued Applications | 617 |
| Pending Applications | 44 |
| Abandoned Applications | 124 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 5437897
[patent_doc_number] => 20090172484
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[patent_title] => ' Method for Implementing a Serialization Construct Within an Environment of Parallel Data Flow Graphs'
[patent_app_type] => utility
[patent_app_number] => 12/330890
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[pdf_file] => publications/A1/0172/20090172484.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/330890 | Implementing a serialization construct within an environment of parallel data flow graphs | Dec 8, 2008 | Issued |
Array
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[patent_doc_number] => 08020127
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[patent_issue_date] => 2011-09-13
[patent_title] => 'Clock frequency exploration for circuit designs having multiple clock domains'
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[patent_app_date] => 2008-11-21
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/275658 | Clock frequency exploration for circuit designs having multiple clock domains | Nov 20, 2008 | Issued |
Array
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[patent_issue_date] => 2009-04-30
[patent_title] => 'Method for designing semiconductor device layout and layout design supporting apparatus'
[patent_app_type] => utility
[patent_app_number] => 12/289198
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[patent_app_date] => 2008-10-22
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[pdf_file] => publications/A1/0113/20090113374.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/289198 | Method for designing semiconductor device layout and layout design supporting apparatus | Oct 21, 2008 | Abandoned |
Array
(
[id] => 6630228
[patent_doc_number] => 20100100856
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[patent_kind] => A1
[patent_issue_date] => 2010-04-22
[patent_title] => 'Automated optimization of an integrated circuit layout using cost functions associated with circuit performance characteristics'
[patent_app_type] => utility
[patent_app_number] => 12/288268
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[patent_app_date] => 2008-10-17
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/288268 | Automated optimization of an integrated circuit layout using cost functions associated with circuit performance characteristics | Oct 16, 2008 | Abandoned |
Array
(
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[patent_issue_date] => 2012-10-02
[patent_title] => 'Method and apparatus for performing lutmask based delay modeling'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/287828 | Method and apparatus for performing lutmask based delay modeling | Oct 13, 2008 | Issued |
Array
(
[id] => 7553292
[patent_doc_number] => 08065634
[patent_country] => US
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[patent_issue_date] => 2011-11-22
[patent_title] => 'System and method for analyzing a nanotube logic circuit'
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[pdf_file] => patents/08/065/08065634.pdf
[firstpage_image] =>[orig_patent_app_number] => 12240409
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/240409 | System and method for analyzing a nanotube logic circuit | Sep 28, 2008 | Issued |
Array
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[patent_doc_number] => 08504960
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[patent_issue_date] => 2013-08-06
[patent_title] => 'Method and system for high speed and low memory footprint static timing analysis'
[patent_app_type] => utility
[patent_app_number] => 12/451308
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/451308 | Method and system for high speed and low memory footprint static timing analysis | May 15, 2008 | Issued |
Array
(
[id] => 6332873
[patent_doc_number] => 20100115488
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-05-06
[patent_title] => 'CIRCUIT DESIGN DEVICE, CIRCUIT DESIGN METHOD, AND CIRCUIT DESIGN PROGRAM'
[patent_app_type] => utility
[patent_app_number] => 12/595828
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[pdf_file] => publications/A1/0115/20100115488.pdf
[firstpage_image] =>[orig_patent_app_number] => 12595828
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/595828 | Circuit design device, circuit design method, and circuit design program | Apr 14, 2008 | Issued |
Array
(
[id] => 5535434
[patent_doc_number] => 20090235222
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-09-17
[patent_title] => 'CREATING A STANDARD CELL CIRCUIT DESIGN FROM A PROGRAMMABLE LOGIC DEVICE CIRCUIT DESIGN'
[patent_app_type] => utility
[patent_app_number] => 12/049676
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/049676 | Creating a standard cell circuit design from a programmable logic device circuit design | Mar 16, 2008 | Issued |
Array
(
[id] => 10834861
[patent_doc_number] => 08863056
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[patent_issue_date] => 2014-10-14
[patent_title] => 'Integrated design-for-manufacturing platform'
[patent_app_type] => utility
[patent_app_number] => 11/844186
[patent_app_country] => US
[patent_app_date] => 2007-08-23
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11844186
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/844186 | Integrated design-for-manufacturing platform | Aug 22, 2007 | Issued |
Array
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[id] => 6652443
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[patent_title] => 'METHOD AND SYSTEM FOR ADAPTING A CIRCUIT LAYOUT TO A PREDEFINED GRID'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/376427 | METHOD AND SYSTEM FOR ADAPTING A CIRCUIT LAYOUT TO A PREDEFINED GRID | Jul 19, 2007 | Abandoned |
Array
(
[id] => 6449678
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[patent_title] => 'TRANSPARENT TEST METHOD AND SCAN FLIP-FLOP'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/303938 | Transparent test method and scan flip-flop | Jun 8, 2007 | Issued |