Search

Eric D. Lee

Examiner (ID: 1963, Phone: (571)270-7098 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2851, 2825
Total Applications
773
Issued Applications
618
Pending Applications
46
Abandoned Applications
125

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18326335 [patent_doc_number] => 20230124463 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-20 [patent_title] => APPARATUS FOR AUTOMATICALLY DETERMINING VEHICLE ELECTRONIC CIRCUIT DIAGRAM [patent_app_type] => utility [patent_app_number] => 17/956256 [patent_app_country] => US [patent_app_date] => 2022-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5337 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17956256 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/956256
Apparatus for automatically determining vehicle electronic circuit diagram Sep 28, 2022 Issued
Array ( [id] => 18271423 [patent_doc_number] => 20230092665 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-23 [patent_title] => USING A MACHINE-TRAINED NETWORK TO PERFORM PHYSICAL DESIGN [patent_app_type] => utility [patent_app_number] => 17/950080 [patent_app_country] => US [patent_app_date] => 2022-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10857 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17950080 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/950080
USING A MACHINE-TRAINED NETWORK TO PERFORM PHYSICAL DESIGN Sep 20, 2022 Pending
Array ( [id] => 19841855 [patent_doc_number] => 12254245 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-18 [patent_title] => Method of processing digitalized drawing data and computer program [patent_app_type] => utility [patent_app_number] => 18/279469 [patent_app_country] => US [patent_app_date] => 2022-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5920 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 255 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18279469 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/279469
Method of processing digitalized drawing data and computer program Sep 14, 2022 Issued
Array ( [id] => 18297032 [patent_doc_number] => 20230106718 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-06 [patent_title] => MULTIPLEXED CHARGE DISCHARGE BATTERY MANAGEMENT SYSTEM [patent_app_type] => utility [patent_app_number] => 17/942260 [patent_app_country] => US [patent_app_date] => 2022-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17401 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17942260 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/942260
Multiplexed charge discharge battery management system Sep 11, 2022 Issued
Array ( [id] => 18111819 [patent_doc_number] => 20230004699 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-05 [patent_title] => SYSTEMS AND METHODS FOR DESIGNING A MODULE SEMICONDUCTOR PRODUCT [patent_app_type] => utility [patent_app_number] => 17/930081 [patent_app_country] => US [patent_app_date] => 2022-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7167 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17930081 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/930081
Systems and methods for designing a module semiconductor product Sep 6, 2022 Issued
Array ( [id] => 19002715 [patent_doc_number] => 20240066786 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-29 [patent_title] => NANOFABRICATION METHOD WITH CORRECTION OF DISTORTION WITHIN AN IMPRINT SYSTEM [patent_app_type] => utility [patent_app_number] => 17/823411 [patent_app_country] => US [patent_app_date] => 2022-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14029 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 253 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17823411 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/823411
Nanofabrication method with correction of distortion within an imprint system Aug 29, 2022 Issued
Array ( [id] => 18471685 [patent_doc_number] => 20230205971 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-29 [patent_title] => METHOD FOR DESIGNING SEMICONDUCTOR INTEGRATED CIRCUIT, CIRCUIT DESIGN SYSTEM, AND CONTROL PROGRAM [patent_app_type] => utility [patent_app_number] => 17/895938 [patent_app_country] => US [patent_app_date] => 2022-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6364 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 254 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17895938 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/895938
Method for designing semiconductor integrated circuit, circuit design system, and control program Aug 24, 2022 Issued
Array ( [id] => 19971547 [patent_doc_number] => 12340162 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2025-06-24 [patent_title] => System and method for electronic design structure connection management [patent_app_type] => utility [patent_app_number] => 17/893357 [patent_app_country] => US [patent_app_date] => 2022-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 1101 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17893357 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/893357
System and method for electronic design structure connection management Aug 22, 2022 Issued
Array ( [id] => 19493394 [patent_doc_number] => 12112110 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-08 [patent_title] => Multi-physics co-simulation method of power semiconductor modules [patent_app_type] => utility [patent_app_number] => 17/890354 [patent_app_country] => US [patent_app_date] => 2022-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8782 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 527 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17890354 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/890354
Multi-physics co-simulation method of power semiconductor modules Aug 17, 2022 Issued
Array ( [id] => 18222126 [patent_doc_number] => 20230061120 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => ROUTING OF HIGH-SPEED, HIGH-THROUGHPUT INTERCONNECTS IN INTEGRATED CIRCUITS [patent_app_type] => utility [patent_app_number] => 17/889903 [patent_app_country] => US [patent_app_date] => 2022-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7030 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17889903 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/889903
Routing of high-speed, high-throughput interconnects in integrated circuits Aug 16, 2022 Issued
Array ( [id] => 18294166 [patent_doc_number] => 20230103852 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-06 [patent_title] => COVER MEMBER AND ELECTRONIC DEVICE INCLUDING THE COVER MEMBER [patent_app_type] => utility [patent_app_number] => 17/888793 [patent_app_country] => US [patent_app_date] => 2022-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17052 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17888793 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/888793
COVER MEMBER AND ELECTRONIC DEVICE INCLUDING THE COVER MEMBER Aug 15, 2022 Pending
Array ( [id] => 19917769 [patent_doc_number] => 12293139 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2025-05-06 [patent_title] => Partitioning a circuit for distributed balanced independent simulation jobs with upper-bounded memory [patent_app_type] => utility [patent_app_number] => 17/879571 [patent_app_country] => US [patent_app_date] => 2022-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4856 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17879571 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/879571
Partitioning a circuit for distributed balanced independent simulation jobs with upper-bounded memory Aug 1, 2022 Issued
Array ( [id] => 18766012 [patent_doc_number] => 11816414 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-14 [patent_title] => Automatic generation of sub-cells for an analog integrated circuit [patent_app_type] => utility [patent_app_number] => 17/815095 [patent_app_country] => US [patent_app_date] => 2022-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 24 [patent_no_of_words] => 8532 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17815095 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/815095
Automatic generation of sub-cells for an analog integrated circuit Jul 25, 2022 Issued
Array ( [id] => 20494488 [patent_doc_number] => 12536360 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-27 [patent_title] => Boundary cell having a common semiconductor type for library cell [patent_app_type] => utility [patent_app_number] => 17/873015 [patent_app_country] => US [patent_app_date] => 2022-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 2188 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17873015 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/873015
Boundary cell having a common semiconductor type for library cell Jul 24, 2022 Issued
Array ( [id] => 19841866 [patent_doc_number] => 12254256 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-18 [patent_title] => Diagnosis of inconsistent constraints in a power intent for an integrated circuit design [patent_app_type] => utility [patent_app_number] => 17/864232 [patent_app_country] => US [patent_app_date] => 2022-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 6621 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17864232 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/864232
Diagnosis of inconsistent constraints in a power intent for an integrated circuit design Jul 12, 2022 Issued
Array ( [id] => 18513607 [patent_doc_number] => 20230229842 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-20 [patent_title] => METHOD OF FABRICATING SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/857680 [patent_app_country] => US [patent_app_date] => 2022-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10400 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17857680 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/857680
Method of fabricating semiconductor device Jul 4, 2022 Issued
Array ( [id] => 18111818 [patent_doc_number] => 20230004698 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-05 [patent_title] => DIVIDING A CHIP DESIGN FLOW INTO SUB-STEPS USING MACHINE LEARNING [patent_app_type] => utility [patent_app_number] => 17/857737 [patent_app_country] => US [patent_app_date] => 2022-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5856 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17857737 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/857737
Dividing a chip design flow into sub-steps using machine learning Jul 4, 2022 Issued
Array ( [id] => 18158696 [patent_doc_number] => 20230025288 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-26 [patent_title] => SYSTEM AND METHOD FOR GENERATION OF A REPORT AND DEBUG OF ADDRESS TRANSFORMATIONS IN ELECTRONIC SYSTEMS DESCRIBED WITH IP-XACT STANDARD [patent_app_type] => utility [patent_app_number] => 17/855806 [patent_app_country] => US [patent_app_date] => 2022-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6339 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17855806 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/855806
System and method for generation of a report and debug of address transformations in electronic systems described with IP-XACT standard Jun 30, 2022 Issued
Array ( [id] => 18881712 [patent_doc_number] => 20240005081 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-04 [patent_title] => METHOD AND SYSTEM TO FACILITATE REVIEW OF SCHEMATICS FOR AN ELECTRONIC DESIGN [patent_app_type] => utility [patent_app_number] => 17/809898 [patent_app_country] => US [patent_app_date] => 2022-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6096 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17809898 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/809898
Method and system to facilitate schematics for an electronic design Jun 29, 2022 Issued
Array ( [id] => 18256688 [patent_doc_number] => 20230083727 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-16 [patent_title] => INTEGRATED CIRCUIT INCLUDING STANDARD CELLS, A METHOD OF DESIGNING A LAYOUT INCLUDING THE SAME, AND A COMPUTING SYSTEM THEREFOR [patent_app_type] => utility [patent_app_number] => 17/841747 [patent_app_country] => US [patent_app_date] => 2022-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8030 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17841747 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/841747
INTEGRATED CIRCUIT INCLUDING STANDARD CELLS, A METHOD OF DESIGNING A LAYOUT INCLUDING THE SAME, AND A COMPUTING SYSTEM THEREFOR Jun 15, 2022 Pending
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