Eric D. Lee

Array ( [id] => 19802882 [patent_doc_number] => 20250068807 [patent_country] => US [patent_kind] => A9 [patent_issue_date] => 2025-02-27 [patent_title] => SYSTEM AND METHOD FOR TRACE GENERATION AND RECONFIGURATION ON A BREADBOARD OR PRINTED CIRCUIT BOARD [patent_app_type] => utility [patent_app_number] => 17/832069 [patent_app_country] => US [patent_app_date] => 2022-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5631 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17832069 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19802882 [patent_doc_number] => 20250068807 [patent_country] => US [patent_kind] => A9 [patent_issue_date] => 2025-02-27 [patent_title] => SYSTEM AND METHOD FOR TRACE GENERATION AND RECONFIGURATION ON A BREADBOARD OR PRINTED CIRCUIT BOARD [patent_app_type] => utility [patent_app_number] => 17/832069 [patent_app_country] => US [patent_app_date] => 2022-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5631 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17832069 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19885956 [patent_doc_number] => 12271673 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-08 [patent_title] => Oscillator layout [patent_app_type] => utility [patent_app_number] => 17/804995 [patent_app_country] => US [patent_app_date] => 2022-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 7423 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17804995 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20079746 [patent_doc_number] => 12353815 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-08 [patent_title] => Method for chip integration [patent_app_type] => utility [patent_app_number] => 17/828648 [patent_app_country] => US [patent_app_date] => 2022-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 1075 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17828648 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18653772 [patent_doc_number] => 20230299614 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-21 [patent_title] => WIRELESS CHARGING AT SUBSTANTIALLY UNIFORM CHARGE RATE FOR DIFFERENT PHYSICAL CHARGE CONFIGURATIONS [patent_app_type] => utility [patent_app_number] => 17/746089 [patent_app_country] => US [patent_app_date] => 2022-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6930 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17746089 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19942522 [patent_doc_number] => 12314654 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2025-05-27 [patent_title] => System and method for electromagnetic modeling in an electronic circuit design [patent_app_type] => utility [patent_app_number] => 17/737449 [patent_app_country] => US [patent_app_date] => 2022-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 28 [patent_no_of_words] => 5728 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17737449 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18067395 [patent_doc_number] => 20220398483 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-15 [patent_title] => QUANTUM SYSTEM CONFIGURED FOR CONDITIONAL TRANSPORT WITH JUST-IN-TIME WAVEFORM SELECTION [patent_app_type] => utility [patent_app_number] => 17/734340 [patent_app_country] => US [patent_app_date] => 2022-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12417 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17734340 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20645323 [patent_doc_number] => 12600254 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-04-14 [patent_title] => Solar charging system for vehicle [patent_app_type] => utility [patent_app_number] => 17/729383 [patent_app_country] => US [patent_app_date] => 2022-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 0 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17729383 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20702717 [patent_doc_number] => 12625426 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-05-12 [patent_title] => Process for creating a three-dimensional structure in a lithography material via a laser lithography device [patent_app_type] => utility [patent_app_number] => 17/712905 [patent_app_country] => US [patent_app_date] => 2022-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 0 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17712905 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18337016 [patent_doc_number] => 20230128965 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-27 [patent_title] => CHARGING METHOD AND DEVICE, TERMINAL DEVICE AND COMPUTER READABLE STORAGE MEDIUM [patent_app_type] => utility [patent_app_number] => 17/703736 [patent_app_country] => US [patent_app_date] => 2022-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10957 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17703736 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17896278 [patent_doc_number] => 20220305940 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-29 [patent_title] => POWER ADJUSTMENT SYSTEM AND AGGREGATION DEVICE [patent_app_type] => utility [patent_app_number] => 17/698359 [patent_app_country] => US [patent_app_date] => 2022-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7251 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17698359 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20188942 [patent_doc_number] => 12400057 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-26 [patent_title] => Hierarchy-aware integrated circuit layout design [patent_app_type] => utility [patent_app_number] => 17/655225 [patent_app_country] => US [patent_app_date] => 2022-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 0 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17655225 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18630606 [patent_doc_number] => 20230289500 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-14 [patent_title] => METHOD AND SYSTEM FOR BUILDING HARDWARE IMAGES FROM HETEROGENEOUS DESIGNS FOR ELETRONIC SYSTEMS [patent_app_type] => utility [patent_app_number] => 17/692602 [patent_app_country] => US [patent_app_date] => 2022-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8368 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17692602 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19167570 [patent_doc_number] => 11983478 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-14 [patent_title] => Selection of full or incremental implementation flows in processing circuit designs [patent_app_type] => utility [patent_app_number] => 17/691771 [patent_app_country] => US [patent_app_date] => 2022-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5059 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17691771 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19427107 [patent_doc_number] => 12086529 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-09-10 [patent_title] => Circuit design modification using timing-based yield calculation [patent_app_type] => utility [patent_app_number] => 17/691974 [patent_app_country] => US [patent_app_date] => 2022-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 9554 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17691974 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18616357 [patent_doc_number] => 20230283096 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-07 [patent_title] => Battery Charging Apparatus and Control Method [patent_app_type] => utility [patent_app_number] => 17/653009 [patent_app_country] => US [patent_app_date] => 2022-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5727 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17653009 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18430720 [patent_doc_number] => 11675942 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-13 [patent_title] => Optimization of parameters for synthesis of a topology using a discriminant function module [patent_app_type] => utility [patent_app_number] => 17/683361 [patent_app_country] => US [patent_app_date] => 2022-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5567 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17683361 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19062103 [patent_doc_number] => 11941339 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-03-26 [patent_title] => Automated equal-resistance routing in compact pattern [patent_app_type] => utility [patent_app_number] => 17/679679 [patent_app_country] => US [patent_app_date] => 2022-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 24 [patent_no_of_words] => 8293 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17679679 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18446280 [patent_doc_number] => 11681852 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-20 [patent_title] => Optimized layout cell [patent_app_type] => utility [patent_app_number] => 17/672137 [patent_app_country] => US [patent_app_date] => 2022-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 7835 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17672137 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19443357 [patent_doc_number] => 12093626 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-17 [patent_title] => Selective extraction of design layout [patent_app_type] => utility [patent_app_number] => 17/671268 [patent_app_country] => US [patent_app_date] => 2022-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6121 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 240 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17671268 [rel_patent_id] =>[rel_patent_doc_number] =>)