Search

Eric D. Lee

Examiner (ID: 19248, Phone: (571)270-7098 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2851, 2825
Total Applications
761
Issued Applications
615
Pending Applications
41
Abandoned Applications
124

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18532167 [patent_doc_number] => 20230237239 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-27 [patent_title] => CIRCUIT UNIT HAVING ADJUSTABLE DRIVING STRENGTH CAPABILITY IN CHIP AND METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/583436 [patent_app_country] => US [patent_app_date] => 2022-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6239 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17583436 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/583436
CIRCUIT UNIT HAVING ADJUSTABLE DRIVING STRENGTH CAPABILITY IN CHIP AND METHOD THEREOF Jan 24, 2022 Pending
Array ( [id] => 17724001 [patent_doc_number] => 20220216723 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-07 [patent_title] => CHARGING SYSTEM AND ELECTRIC VEHICLE [patent_app_type] => utility [patent_app_number] => 17/579935 [patent_app_country] => US [patent_app_date] => 2022-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17747 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 295 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17579935 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/579935
Charging system and electric vehicle Jan 19, 2022 Issued
Array ( [id] => 18873468 [patent_doc_number] => 11861279 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-01-02 [patent_title] => Computer-aided design tool for inverter minimization [patent_app_type] => utility [patent_app_number] => 17/648406 [patent_app_country] => US [patent_app_date] => 2022-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 43 [patent_figures_cnt] => 43 [patent_no_of_words] => 37423 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17648406 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/648406
Computer-aided design tool for inverter minimization Jan 18, 2022 Issued
Array ( [id] => 17581534 [patent_doc_number] => 20220138389 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-05 [patent_title] => DETECTING OUT-OF-BOUNDS VIOLATIONS IN A HARDWARE DESIGN USING FORMAL VERIFICATION [patent_app_type] => utility [patent_app_number] => 17/573611 [patent_app_country] => US [patent_app_date] => 2022-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13711 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17573611 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/573611
Detecting out-of-bounds violations in a hardware design using formal verification Jan 10, 2022 Issued
Array ( [id] => 18734953 [patent_doc_number] => 11803687 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-10-31 [patent_title] => Interactive cross-section parameterized cell for wire in circuit design [patent_app_type] => utility [patent_app_number] => 17/573380 [patent_app_country] => US [patent_app_date] => 2022-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9399 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17573380 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/573380
Interactive cross-section parameterized cell for wire in circuit design Jan 10, 2022 Issued
Array ( [id] => 18155146 [patent_doc_number] => 11568127 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-31 [patent_title] => Mask rule checking for curvilinear masks for electronic circuits [patent_app_type] => utility [patent_app_number] => 17/572201 [patent_app_country] => US [patent_app_date] => 2022-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 26 [patent_no_of_words] => 12367 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17572201 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/572201
Mask rule checking for curvilinear masks for electronic circuits Jan 9, 2022 Issued
Array ( [id] => 17565465 [patent_doc_number] => 20220129614 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-28 [patent_title] => METHOD AND SYSTEM OF FORMING SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/568993 [patent_app_country] => US [patent_app_date] => 2022-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6995 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17568993 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/568993
Method and system of forming semiconductor device Jan 4, 2022 Issued
Array ( [id] => 17707216 [patent_doc_number] => 20220207222 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-30 [patent_title] => INTERACTIVE SYSTEM FOR GUIDING ELECTRONICS DESIGN AND ASSEMBLY [patent_app_type] => utility [patent_app_number] => 17/568569 [patent_app_country] => US [patent_app_date] => 2022-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13512 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17568569 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/568569
INTERACTIVE SYSTEM FOR GUIDING ELECTRONICS DESIGN AND ASSEMBLY Jan 3, 2022 Abandoned
Array ( [id] => 19107704 [patent_doc_number] => 11960813 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-16 [patent_title] => Automatic redistribution layer via generation [patent_app_type] => utility [patent_app_number] => 17/562833 [patent_app_country] => US [patent_app_date] => 2021-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8040 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17562833 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/562833
Automatic redistribution layer via generation Dec 26, 2021 Issued
Array ( [id] => 19626005 [patent_doc_number] => 12164838 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-12-10 [patent_title] => Intelligent drawing-model checking method and apparatus [patent_app_type] => utility [patent_app_number] => 18/690750 [patent_app_country] => US [patent_app_date] => 2021-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 12131 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18690750 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/690750
Intelligent drawing-model checking method and apparatus Dec 23, 2021 Issued
Array ( [id] => 18974289 [patent_doc_number] => 20240054381 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-15 [patent_title] => CONTROL SYSTEM FOR A STATE OF A QUANTUM HARMONIC OSCILLATOR [patent_app_type] => utility [patent_app_number] => 18/268238 [patent_app_country] => US [patent_app_date] => 2021-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4929 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18268238 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/268238
Control system for a state of a quantum harmonic oscillator Dec 15, 2021 Issued
Array ( [id] => 18422783 [patent_doc_number] => 20230177247 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-08 [patent_title] => THREE-DIMENSIONAL ROUGHNESS EXTRACTION OF METAL [patent_app_type] => utility [patent_app_number] => 17/542882 [patent_app_country] => US [patent_app_date] => 2021-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5261 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17542882 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/542882
THREE-DIMENSIONAL ROUGHNESS EXTRACTION OF METAL Dec 5, 2021 Pending
Array ( [id] => 19427103 [patent_doc_number] => 12086525 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-10 [patent_title] => Electrically aware routing for integrated circuits [patent_app_type] => utility [patent_app_number] => 17/543443 [patent_app_country] => US [patent_app_date] => 2021-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 12279 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17543443 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/543443
Electrically aware routing for integrated circuits Dec 5, 2021 Issued
Array ( [id] => 18889925 [patent_doc_number] => 11868698 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-01-09 [patent_title] => Context-aware circuit design layout construct [patent_app_type] => utility [patent_app_number] => 17/541171 [patent_app_country] => US [patent_app_date] => 2021-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10338 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17541171 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/541171
Context-aware circuit design layout construct Dec 1, 2021 Issued
Array ( [id] => 17659575 [patent_doc_number] => 20220180040 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-09 [patent_title] => METHOD OF DETECTING DEFECTIVE LAYER OF SEMICONDUCTOR DEVICE AND COMPUTING SYSTEM FOR PERFORMING THE SAME [patent_app_type] => utility [patent_app_number] => 17/539697 [patent_app_country] => US [patent_app_date] => 2021-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7577 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17539697 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/539697
Method of detecting defective layer of semiconductor device and computing system for performing the same Nov 30, 2021 Issued
Array ( [id] => 17476216 [patent_doc_number] => 20220083720 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-17 [patent_title] => ELECTRICAL CIRCUIT DESIGN [patent_app_type] => utility [patent_app_number] => 17/538961 [patent_app_country] => US [patent_app_date] => 2021-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19759 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 257 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17538961 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/538961
Electrical circuit design Nov 29, 2021 Issued
Array ( [id] => 18703633 [patent_doc_number] => 11790147 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-10-17 [patent_title] => System and method for routing in an electronic design [patent_app_type] => utility [patent_app_number] => 17/532087 [patent_app_country] => US [patent_app_date] => 2021-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 5415 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17532087 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/532087
System and method for routing in an electronic design Nov 21, 2021 Issued
Array ( [id] => 19015172 [patent_doc_number] => 11922105 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-03-05 [patent_title] => Computer-aided design tool for minimum gate count initialization [patent_app_type] => utility [patent_app_number] => 17/523572 [patent_app_country] => US [patent_app_date] => 2021-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 43 [patent_figures_cnt] => 43 [patent_no_of_words] => 37528 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17523572 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/523572
Computer-aided design tool for minimum gate count initialization Nov 9, 2021 Issued
Array ( [id] => 19971658 [patent_doc_number] => 12340273 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-24 [patent_title] => Quantum processor unit architecture for quantum computing via an arbitrarily programmable interaction connectivity graph [patent_app_type] => utility [patent_app_number] => 17/519320 [patent_app_country] => US [patent_app_date] => 2021-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 4501 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17519320 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/519320
Quantum processor unit architecture for quantum computing via an arbitrarily programmable interaction connectivity graph Nov 3, 2021 Issued
Array ( [id] => 18873467 [patent_doc_number] => 11861278 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-01-02 [patent_title] => Computer-aided design tool for gate pruning [patent_app_type] => utility [patent_app_number] => 17/515012 [patent_app_country] => US [patent_app_date] => 2021-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 43 [patent_figures_cnt] => 43 [patent_no_of_words] => 35984 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17515012 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/515012
Computer-aided design tool for gate pruning Oct 28, 2021 Issued
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