Search

Eric D. Lee

Examiner (ID: 17546)

Most Active Art Unit
2851
Art Unit(s)
2851, 2825
Total Applications
769
Issued Applications
617
Pending Applications
44
Abandoned Applications
124

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17962469 [patent_doc_number] => 20220343050 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-27 [patent_title] => UHD HDR IP CLIENT DEVICE PCB DESIGN LAYOUT [patent_app_type] => utility [patent_app_number] => 17/669764 [patent_app_country] => US [patent_app_date] => 2022-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4415 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 436 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17669764 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/669764
UHD HDR IP client device PCB design layout Feb 10, 2022 Issued
Array ( [id] => 17809689 [patent_doc_number] => 20220261524 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-18 [patent_title] => IN-GRAPH CAUSALITY RANKING FOR FAULTS IN THE DESIGN OF INTEGRATED CIRCUITS [patent_app_type] => utility [patent_app_number] => 17/669307 [patent_app_country] => US [patent_app_date] => 2022-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7445 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17669307 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/669307
In-graph causality ranking for faults in the design of integrated circuits Feb 9, 2022 Issued
Array ( [id] => 17832666 [patent_doc_number] => 20220269970 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-25 [patent_title] => QUANTUM CIRCUIT AND QUANTUM PROCESSOR [patent_app_type] => utility [patent_app_number] => 17/668380 [patent_app_country] => US [patent_app_date] => 2022-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6533 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17668380 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/668380
Quantum circuit and quantum processor Feb 8, 2022 Issued
Array ( [id] => 20441906 [patent_doc_number] => 12512748 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-30 [patent_title] => Electrical assembly [patent_app_type] => utility [patent_app_number] => 17/668072 [patent_app_country] => US [patent_app_date] => 2022-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 2169 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17668072 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/668072
Electrical assembly Feb 8, 2022 Issued
Array ( [id] => 19243684 [patent_doc_number] => 12014127 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-18 [patent_title] => Transforming a logical netlist into a hierarchical parasitic netlist [patent_app_type] => utility [patent_app_number] => 17/668180 [patent_app_country] => US [patent_app_date] => 2022-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 9305 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17668180 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/668180
Transforming a logical netlist into a hierarchical parasitic netlist Feb 8, 2022 Issued
Array ( [id] => 19062098 [patent_doc_number] => 11941334 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-03-26 [patent_title] => System and method for intelligent intent recognition based electronic design [patent_app_type] => utility [patent_app_number] => 17/665670 [patent_app_country] => US [patent_app_date] => 2022-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 4636 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17665670 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/665670
System and method for intelligent intent recognition based electronic design Feb 6, 2022 Issued
Array ( [id] => 18539739 [patent_doc_number] => 20230244847 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-03 [patent_title] => NEW RELEASE PROCESS INCLUDING CONSISTENCY CHECKING [patent_app_type] => utility [patent_app_number] => 17/591111 [patent_app_country] => US [patent_app_date] => 2022-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6037 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17591111 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/591111
NEW RELEASE PROCESS INCLUDING CONSISTENCY CHECKING Feb 1, 2022 Abandoned
Array ( [id] => 18532167 [patent_doc_number] => 20230237239 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-27 [patent_title] => CIRCUIT UNIT HAVING ADJUSTABLE DRIVING STRENGTH CAPABILITY IN CHIP AND METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/583436 [patent_app_country] => US [patent_app_date] => 2022-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6239 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17583436 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/583436
CIRCUIT UNIT HAVING ADJUSTABLE DRIVING STRENGTH CAPABILITY IN CHIP AND METHOD THEREOF Jan 24, 2022 Pending
Array ( [id] => 17724001 [patent_doc_number] => 20220216723 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-07 [patent_title] => CHARGING SYSTEM AND ELECTRIC VEHICLE [patent_app_type] => utility [patent_app_number] => 17/579935 [patent_app_country] => US [patent_app_date] => 2022-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17747 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 295 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17579935 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/579935
Charging system and electric vehicle Jan 19, 2022 Issued
Array ( [id] => 18873468 [patent_doc_number] => 11861279 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-01-02 [patent_title] => Computer-aided design tool for inverter minimization [patent_app_type] => utility [patent_app_number] => 17/648406 [patent_app_country] => US [patent_app_date] => 2022-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 43 [patent_figures_cnt] => 43 [patent_no_of_words] => 37423 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17648406 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/648406
Computer-aided design tool for inverter minimization Jan 18, 2022 Issued
Array ( [id] => 17581534 [patent_doc_number] => 20220138389 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-05 [patent_title] => DETECTING OUT-OF-BOUNDS VIOLATIONS IN A HARDWARE DESIGN USING FORMAL VERIFICATION [patent_app_type] => utility [patent_app_number] => 17/573611 [patent_app_country] => US [patent_app_date] => 2022-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13711 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17573611 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/573611
Detecting out-of-bounds violations in a hardware design using formal verification Jan 10, 2022 Issued
Array ( [id] => 18734953 [patent_doc_number] => 11803687 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-10-31 [patent_title] => Interactive cross-section parameterized cell for wire in circuit design [patent_app_type] => utility [patent_app_number] => 17/573380 [patent_app_country] => US [patent_app_date] => 2022-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9399 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17573380 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/573380
Interactive cross-section parameterized cell for wire in circuit design Jan 10, 2022 Issued
Array ( [id] => 18155146 [patent_doc_number] => 11568127 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-31 [patent_title] => Mask rule checking for curvilinear masks for electronic circuits [patent_app_type] => utility [patent_app_number] => 17/572201 [patent_app_country] => US [patent_app_date] => 2022-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 26 [patent_no_of_words] => 12367 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17572201 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/572201
Mask rule checking for curvilinear masks for electronic circuits Jan 9, 2022 Issued
Array ( [id] => 17565465 [patent_doc_number] => 20220129614 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-28 [patent_title] => METHOD AND SYSTEM OF FORMING SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/568993 [patent_app_country] => US [patent_app_date] => 2022-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6995 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17568993 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/568993
Method and system of forming semiconductor device Jan 4, 2022 Issued
Array ( [id] => 17707216 [patent_doc_number] => 20220207222 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-30 [patent_title] => INTERACTIVE SYSTEM FOR GUIDING ELECTRONICS DESIGN AND ASSEMBLY [patent_app_type] => utility [patent_app_number] => 17/568569 [patent_app_country] => US [patent_app_date] => 2022-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13512 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17568569 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/568569
INTERACTIVE SYSTEM FOR GUIDING ELECTRONICS DESIGN AND ASSEMBLY Jan 3, 2022 Abandoned
Array ( [id] => 19107704 [patent_doc_number] => 11960813 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-16 [patent_title] => Automatic redistribution layer via generation [patent_app_type] => utility [patent_app_number] => 17/562833 [patent_app_country] => US [patent_app_date] => 2021-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8040 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17562833 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/562833
Automatic redistribution layer via generation Dec 26, 2021 Issued
Array ( [id] => 19626005 [patent_doc_number] => 12164838 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-12-10 [patent_title] => Intelligent drawing-model checking method and apparatus [patent_app_type] => utility [patent_app_number] => 18/690750 [patent_app_country] => US [patent_app_date] => 2021-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 12131 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18690750 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/690750
Intelligent drawing-model checking method and apparatus Dec 23, 2021 Issued
Array ( [id] => 18974289 [patent_doc_number] => 20240054381 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-15 [patent_title] => CONTROL SYSTEM FOR A STATE OF A QUANTUM HARMONIC OSCILLATOR [patent_app_type] => utility [patent_app_number] => 18/268238 [patent_app_country] => US [patent_app_date] => 2021-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4929 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18268238 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/268238
Control system for a state of a quantum harmonic oscillator Dec 15, 2021 Issued
Array ( [id] => 19427103 [patent_doc_number] => 12086525 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-10 [patent_title] => Electrically aware routing for integrated circuits [patent_app_type] => utility [patent_app_number] => 17/543443 [patent_app_country] => US [patent_app_date] => 2021-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 12279 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17543443 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/543443
Electrically aware routing for integrated circuits Dec 5, 2021 Issued
Array ( [id] => 18422783 [patent_doc_number] => 20230177247 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-08 [patent_title] => THREE-DIMENSIONAL ROUGHNESS EXTRACTION OF METAL [patent_app_type] => utility [patent_app_number] => 17/542882 [patent_app_country] => US [patent_app_date] => 2021-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5261 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17542882 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/542882
THREE-DIMENSIONAL ROUGHNESS EXTRACTION OF METAL Dec 5, 2021 Pending
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