Eric D. Lee

Array ( [id] => 19015172 [patent_doc_number] => 11922105 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-03-05 [patent_title] => Computer-aided design tool for minimum gate count initialization [patent_app_type] => utility [patent_app_number] => 17/523572 [patent_app_country] => US [patent_app_date] => 2021-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 43 [patent_figures_cnt] => 43 [patent_no_of_words] => 37528 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17523572 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19971658 [patent_doc_number] => 12340273 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-24 [patent_title] => Quantum processor unit architecture for quantum computing via an arbitrarily programmable interaction connectivity graph [patent_app_type] => utility [patent_app_number] => 17/519320 [patent_app_country] => US [patent_app_date] => 2021-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 4501 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17519320 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19971658 [patent_doc_number] => 12340273 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-24 [patent_title] => Quantum processor unit architecture for quantum computing via an arbitrarily programmable interaction connectivity graph [patent_app_type] => utility [patent_app_number] => 17/519320 [patent_app_country] => US [patent_app_date] => 2021-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 4501 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17519320 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18873467 [patent_doc_number] => 11861278 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-01-02 [patent_title] => Computer-aided design tool for gate pruning [patent_app_type] => utility [patent_app_number] => 17/515012 [patent_app_country] => US [patent_app_date] => 2021-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 43 [patent_figures_cnt] => 43 [patent_no_of_words] => 35984 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17515012 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19122694 [patent_doc_number] => 11966683 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-23 [patent_title] => Method and system for comprehensively evaluating reliability of multi-chip parallel IGBT module [patent_app_type] => utility [patent_app_number] => 17/503396 [patent_app_country] => US [patent_app_date] => 2021-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 5290 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17503396 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18856082 [patent_doc_number] => 11853666 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-12-26 [patent_title] => Computer-aided design tool for wide-input logic initialization [patent_app_type] => utility [patent_app_number] => 17/503014 [patent_app_country] => US [patent_app_date] => 2021-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 43 [patent_figures_cnt] => 43 [patent_no_of_words] => 37360 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17503014 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19443362 [patent_doc_number] => 12093631 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-17 [patent_title] => Method, system and verifying platform for system on chip verification [patent_app_type] => utility [patent_app_number] => 17/500768 [patent_app_country] => US [patent_app_date] => 2021-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5446 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 278 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17500768 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18308024 [patent_doc_number] => 20230111924 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-13 [patent_title] => FUNCTIONAL-LEVEL PROCESSING COMPONENT FOR QUANTUM COMPUTERS [patent_app_type] => utility [patent_app_number] => 17/450584 [patent_app_country] => US [patent_app_date] => 2021-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 28809 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17450584 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18766007 [patent_doc_number] => 11816409 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-11-14 [patent_title] => Strongly connected component (SCC) graph representation for interactive analysis of overlapping loops in emulation and prototyping [patent_app_type] => utility [patent_app_number] => 17/498658 [patent_app_country] => US [patent_app_date] => 2021-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 10691 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17498658 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18750487 [patent_doc_number] => 11809801 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-11-07 [patent_title] => Computer-aided design tool for circuit logic initialization [patent_app_type] => utility [patent_app_number] => 17/497554 [patent_app_country] => US [patent_app_date] => 2021-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 43 [patent_figures_cnt] => 43 [patent_no_of_words] => 36456 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17497554 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18703635 [patent_doc_number] => 11790149 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-10-17 [patent_title] => System and method for tracing nets across multiple fabrics in an electronic design [patent_app_type] => utility [patent_app_number] => 17/496660 [patent_app_country] => US [patent_app_date] => 2021-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 20 [patent_no_of_words] => 4872 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17496660 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18881821 [patent_doc_number] => 20240005190 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-04 [patent_title] => METHOD, APPARATUS, TERMINAL AND STORAGE MEDIUM FOR QUANTUM TOPOLOGY GRAPH OPTIMIZATION [patent_app_type] => utility [patent_app_number] => 18/029569 [patent_app_country] => US [patent_app_date] => 2021-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 55875 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18029569 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18282626 [patent_doc_number] => 20230098098 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-30 [patent_title] => SCALABLE SCRIBE REGIONS FOR IMPLEMENTING USER CIRCUIT DESIGNS IN AN INTEGRATED CIRCUIT USING DYNAMIC FUNCTION EXCHANGE [patent_app_type] => utility [patent_app_number] => 17/487781 [patent_app_country] => US [patent_app_date] => 2021-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13827 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17487781 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18293879 [patent_doc_number] => 20230103565 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-06 [patent_title] => REGISTER TRANSFER LEVEL NAVIGATION MICROSERVICES AND INSTRUMENTATION FOR CLOUD-NATIVE ELECTRONIC DESIGN AUTOMATION (EDA) PLATFORMS [patent_app_type] => utility [patent_app_number] => 17/487423 [patent_app_country] => US [patent_app_date] => 2021-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10575 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17487423 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17508064 [patent_doc_number] => 20220101167 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-31 [patent_title] => Hybrid Quantum Computation Architecture for Solving Quadratic Unconstrained Binary Optimization Problems [patent_app_type] => utility [patent_app_number] => 17/482288 [patent_app_country] => US [patent_app_date] => 2021-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10776 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -2 [patent_words_short_claim] => 26 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17482288 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17508064 [patent_doc_number] => 20220101167 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-31 [patent_title] => Hybrid Quantum Computation Architecture for Solving Quadratic Unconstrained Binary Optimization Problems [patent_app_type] => utility [patent_app_number] => 17/482288 [patent_app_country] => US [patent_app_date] => 2021-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10776 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -2 [patent_words_short_claim] => 26 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17482288 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18204396 [patent_doc_number] => 11586791 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-02-21 [patent_title] => Visualization of data buses in circuit designs [patent_app_type] => utility [patent_app_number] => 17/480389 [patent_app_country] => US [patent_app_date] => 2021-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5063 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17480389 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18950039 [patent_doc_number] => 11893335 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-02-06 [patent_title] => System and method for routing in an electronic design [patent_app_type] => utility [patent_app_number] => 17/477855 [patent_app_country] => US [patent_app_date] => 2021-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 37 [patent_no_of_words] => 4482 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17477855 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18766006 [patent_doc_number] => 11816408 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-11-14 [patent_title] => Computer-aided design tool for majority or minority inverter graph synthesis [patent_app_type] => utility [patent_app_number] => 17/478688 [patent_app_country] => US [patent_app_date] => 2021-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 43 [patent_figures_cnt] => 43 [patent_no_of_words] => 36362 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17478688 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18227036 [patent_doc_number] => 20230066030 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => CALIBRATION METHOD FOR EMULATING GROUP III-V SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING GROUP III-V SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/462747 [patent_app_country] => US [patent_app_date] => 2021-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5652 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17462747 [rel_patent_id] =>[rel_patent_doc_number] =>)