Search

Eric D. Lee

Examiner (ID: 16720, Phone: (571)270-7098 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2851, 2825
Total Applications
750
Issued Applications
606
Pending Applications
38
Abandoned Applications
124

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18226848 [patent_doc_number] => 20230065842 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => PREDICTION AND OPTIMIZATION OF MULTI-KERNEL CIRCUIT DESIGN PERFORMANCE USING A PROGRAMMABLE OVERLAY [patent_app_type] => utility [patent_app_number] => 17/411484 [patent_app_country] => US [patent_app_date] => 2021-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14064 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17411484 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/411484
Prediction and optimization of multi-kernel circuit design performance using a programmable overlay Aug 24, 2021 Issued
Array ( [id] => 17751756 [patent_doc_number] => 20220229961 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-21 [patent_title] => Systems and Methods for Programming Electrical Fuse [patent_app_type] => utility [patent_app_number] => 17/411262 [patent_app_country] => US [patent_app_date] => 2021-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4061 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17411262 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/411262
Systems and Methods for Programming Electrical Fuse Aug 24, 2021 Pending
Array ( [id] => 18547382 [patent_doc_number] => 11720735 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-08 [patent_title] => Flat shell for an accelerator card [patent_app_type] => utility [patent_app_number] => 17/408218 [patent_app_country] => US [patent_app_date] => 2021-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 8473 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17408218 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/408218
Flat shell for an accelerator card Aug 19, 2021 Issued
Array ( [id] => 18330997 [patent_doc_number] => 11636243 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-04-25 [patent_title] => Method and system for recording integrated circuit version [patent_app_type] => utility [patent_app_number] => 17/407378 [patent_app_country] => US [patent_app_date] => 2021-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3174 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17407378 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/407378
Method and system for recording integrated circuit version Aug 19, 2021 Issued
Array ( [id] => 17886624 [patent_doc_number] => 20220302102 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-22 [patent_title] => MODELING METHOD [patent_app_type] => utility [patent_app_number] => 17/403556 [patent_app_country] => US [patent_app_date] => 2021-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6333 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17403556 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/403556
Modeling method Aug 15, 2021 Issued
Array ( [id] => 18053266 [patent_doc_number] => 11526651 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-12-13 [patent_title] => Predictive antenna diode insertion in a macro having a clock mesh [patent_app_type] => utility [patent_app_number] => 17/400556 [patent_app_country] => US [patent_app_date] => 2021-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5062 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17400556 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/400556
Predictive antenna diode insertion in a macro having a clock mesh Aug 11, 2021 Issued
Array ( [id] => 17446759 [patent_doc_number] => 20220067264 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-03 [patent_title] => CHIP DESIGN METHOD, DESIGN DEVICE, COMPUTER DEVICE AND STORAGE MEDIUM [patent_app_type] => utility [patent_app_number] => 17/398220 [patent_app_country] => US [patent_app_date] => 2021-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7543 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17398220 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/398220
CHIP DESIGN METHOD, DESIGN DEVICE, COMPUTER DEVICE AND STORAGE MEDIUM Aug 9, 2021 Abandoned
Array ( [id] => 17581542 [patent_doc_number] => 20220138397 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-05 [patent_title] => SEMICONDUCTOR DESIGN AUTOMATION SYSTEM AND COMPUTING SYSTEM INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 17/395594 [patent_app_country] => US [patent_app_date] => 2021-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6224 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17395594 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/395594
Semiconductor design automation system and computing system including the same Aug 5, 2021 Issued
Array ( [id] => 18059745 [patent_doc_number] => 20220390831 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-08 [patent_title] => SYSTEMS AND METHODS FOR IDENTIFICATION AND ELIMINATION OF GEOMETRICAL DESIGN RULE VIOLATIONS OF A MASK LAYOUT BLOCK [patent_app_type] => utility [patent_app_number] => 17/391292 [patent_app_country] => US [patent_app_date] => 2021-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6996 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17391292 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/391292
Systems and methods for identification and elimination of geometrical design rule violations of a mask layout block Aug 1, 2021 Issued
Array ( [id] => 18104543 [patent_doc_number] => 11544433 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-01-03 [patent_title] => Virtual repeater insertion [patent_app_type] => utility [patent_app_number] => 17/389570 [patent_app_country] => US [patent_app_date] => 2021-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 15071 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 301 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17389570 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/389570
Virtual repeater insertion Jul 29, 2021 Issued
Array ( [id] => 18607069 [patent_doc_number] => 11748537 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-09-05 [patent_title] => Computer-aided design tool for logic synthesis of a mix of CMOS gates and majority and minority logic circuits [patent_app_type] => utility [patent_app_number] => 17/384626 [patent_app_country] => US [patent_app_date] => 2021-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 43 [patent_figures_cnt] => 43 [patent_no_of_words] => 37202 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17384626 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/384626
Computer-aided design tool for logic synthesis of a mix of CMOS gates and majority and minority logic circuits Jul 22, 2021 Issued
Array ( [id] => 19122186 [patent_doc_number] => 11966166 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-23 [patent_title] => Measurement apparatus and a method for determining a substrate grid [patent_app_type] => utility [patent_app_number] => 17/377648 [patent_app_country] => US [patent_app_date] => 2021-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 14414 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17377648 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/377648
Measurement apparatus and a method for determining a substrate grid Jul 15, 2021 Issued
Array ( [id] => 19375767 [patent_doc_number] => 12067337 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-20 [patent_title] => Power grid, IC and method for placing power grid [patent_app_type] => utility [patent_app_number] => 17/377635 [patent_app_country] => US [patent_app_date] => 2021-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7554 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17377635 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/377635
Power grid, IC and method for placing power grid Jul 15, 2021 Issued
Array ( [id] => 17778966 [patent_doc_number] => 20220245316 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-04 [patent_title] => COMPUTER-IMPLEMENTED METHOD OF PERFORMING VOLTAGE RULE CHECK IN AN ELECTRONIC DESIGN AUTOMATION PLATFORM [patent_app_type] => utility [patent_app_number] => 17/373790 [patent_app_country] => US [patent_app_date] => 2021-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5224 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17373790 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/373790
Computer-implemented method of performing voltage rule check in an electronic design automation platform Jul 12, 2021 Issued
Array ( [id] => 18047010 [patent_doc_number] => 11520966 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-12-06 [patent_title] => Automated assisted circuit validation [patent_app_type] => utility [patent_app_number] => 17/370976 [patent_app_country] => US [patent_app_date] => 2021-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 7066 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17370976 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/370976
Automated assisted circuit validation Jul 7, 2021 Issued
Array ( [id] => 19212856 [patent_doc_number] => 12001919 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-06-04 [patent_title] => Frequency selective photon dissipation for an energy gap protected qubit [patent_app_type] => utility [patent_app_number] => 17/364813 [patent_app_country] => US [patent_app_date] => 2021-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 8120 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17364813 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/364813
Frequency selective photon dissipation for an energy gap protected qubit Jun 29, 2021 Issued
Array ( [id] => 17172830 [patent_doc_number] => 20210326500 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-21 [patent_title] => GENERATION OF DYNAMIC DESIGN FLOWS FOR INTEGRATED CIRCUITS [patent_app_type] => utility [patent_app_number] => 17/361253 [patent_app_country] => US [patent_app_date] => 2021-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 26916 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17361253 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/361253
Generation of dynamic design flows for integrated circuits Jun 27, 2021 Issued
Array ( [id] => 18262334 [patent_doc_number] => 11610036 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-03-21 [patent_title] => Integrated circuits as a service [patent_app_type] => utility [patent_app_number] => 17/361238 [patent_app_country] => US [patent_app_date] => 2021-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 19138 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17361238 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/361238
Integrated circuits as a service Jun 27, 2021 Issued
Array ( [id] => 17622254 [patent_doc_number] => 11341311 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-05-24 [patent_title] => Generation and selection of universally routable via mesh specifications in an integrated circuit [patent_app_type] => utility [patent_app_number] => 17/356709 [patent_app_country] => US [patent_app_date] => 2021-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 7732 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17356709 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/356709
Generation and selection of universally routable via mesh specifications in an integrated circuit Jun 23, 2021 Issued
Array ( [id] => 18316855 [patent_doc_number] => 11630937 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-04-18 [patent_title] => System and method for predictive 3-D virtual fabrication [patent_app_type] => utility [patent_app_number] => 17/355533 [patent_app_country] => US [patent_app_date] => 2021-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 43 [patent_no_of_words] => 13758 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 255 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17355533 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/355533
System and method for predictive 3-D virtual fabrication Jun 22, 2021 Issued
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