Search

Eric D. Lee

Examiner (ID: 16720, Phone: (571)270-7098 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2851, 2825
Total Applications
750
Issued Applications
606
Pending Applications
38
Abandoned Applications
124

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19828064 [patent_doc_number] => 12248848 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-11 [patent_title] => Scalable gate control in quantum circuit assemblies [patent_app_type] => utility [patent_app_number] => 17/340173 [patent_app_country] => US [patent_app_date] => 2021-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 45 [patent_no_of_words] => 31864 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17340173 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/340173
Scalable gate control in quantum circuit assemblies Jun 6, 2021 Issued
Array ( [id] => 17637191 [patent_doc_number] => 11347915 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-05-31 [patent_title] => System and method for objective probing and generation of timing constraints associated with an electronic circuit design [patent_app_type] => utility [patent_app_number] => 17/338033 [patent_app_country] => US [patent_app_date] => 2021-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5918 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17338033 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/338033
System and method for objective probing and generation of timing constraints associated with an electronic circuit design Jun 2, 2021 Issued
Array ( [id] => 18038954 [patent_doc_number] => 20220383170 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-01 [patent_title] => SYNCHRONIZING OPERATION OF CONTROL CIRCUITS IN A QUANTUM CIRCUIT ASSEMBLY [patent_app_type] => utility [patent_app_number] => 17/332182 [patent_app_country] => US [patent_app_date] => 2021-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 25628 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17332182 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/332182
SYNCHRONIZING OPERATION OF CONTROL CIRCUITS IN A QUANTUM CIRCUIT ASSEMBLY May 26, 2021 Abandoned
Array ( [id] => 17247387 [patent_doc_number] => 20210367132 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-25 [patent_title] => DRIVING CIRCUIT AND DRIVING METHOD [patent_app_type] => utility [patent_app_number] => 17/325922 [patent_app_country] => US [patent_app_date] => 2021-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14300 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17325922 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/325922
Driving circuit and driving method May 19, 2021 Issued
Array ( [id] => 17528917 [patent_doc_number] => 11301606 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-04-12 [patent_title] => Counting method for counting the stage number passing through a signal path on a graphical user interface [patent_app_type] => utility [patent_app_number] => 17/317009 [patent_app_country] => US [patent_app_date] => 2021-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4043 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17317009 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/317009
Counting method for counting the stage number passing through a signal path on a graphical user interface May 10, 2021 Issued
Array ( [id] => 17024429 [patent_doc_number] => 20210248301 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-12 [patent_title] => PUZZLE-BASED PATTERN ANALYSIS AND CLASSIFICATION [patent_app_type] => utility [patent_app_number] => 17/245834 [patent_app_country] => US [patent_app_date] => 2021-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12642 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17245834 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/245834
Puzzle-based pattern analysis and classification Apr 29, 2021 Issued
Array ( [id] => 17771504 [patent_doc_number] => 11403447 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-08-02 [patent_title] => Runtime intellectual property core metadata to rebuild a next-compile-time intellectual property core [patent_app_type] => utility [patent_app_number] => 17/243730 [patent_app_country] => US [patent_app_date] => 2021-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 10056 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17243730 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/243730
Runtime intellectual property core metadata to rebuild a next-compile-time intellectual property core Apr 28, 2021 Issued
Array ( [id] => 18019969 [patent_doc_number] => 20220371468 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-24 [patent_title] => THE METHOD OF PARKING AND CHARGING THE VEHICLE [patent_app_type] => utility [patent_app_number] => 17/765641 [patent_app_country] => US [patent_app_date] => 2021-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8421 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17765641 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/765641
THE METHOD OF PARKING AND CHARGING THE VEHICLE Apr 28, 2021 Pending
Array ( [id] => 18119584 [patent_doc_number] => 11550979 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-10 [patent_title] => Implementing and verifying safety measures in a system design based on safety specification generated from safety requirements [patent_app_type] => utility [patent_app_number] => 17/235802 [patent_app_country] => US [patent_app_date] => 2021-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8252 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17235802 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/235802
Implementing and verifying safety measures in a system design based on safety specification generated from safety requirements Apr 19, 2021 Issued
Array ( [id] => 19259906 [patent_doc_number] => 12019965 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-25 [patent_title] => Integrated circuit including standard cell and method of manufacturing the integrated circuit [patent_app_type] => utility [patent_app_number] => 17/225773 [patent_app_country] => US [patent_app_date] => 2021-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8237 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17225773 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/225773
Integrated circuit including standard cell and method of manufacturing the integrated circuit Apr 7, 2021 Issued
Array ( [id] => 19740143 [patent_doc_number] => 12216978 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-04 [patent_title] => Routing structure of semiconductor device and forming method thereof [patent_app_type] => utility [patent_app_number] => 17/225903 [patent_app_country] => US [patent_app_date] => 2021-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 11076 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 283 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17225903 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/225903
Routing structure of semiconductor device and forming method thereof Apr 7, 2021 Issued
Array ( [id] => 18155145 [patent_doc_number] => 11568126 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-31 [patent_title] => Integrated circuit device design method and system [patent_app_type] => utility [patent_app_number] => 17/223612 [patent_app_country] => US [patent_app_date] => 2021-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7894 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17223612 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/223612
Integrated circuit device design method and system Apr 5, 2021 Issued
Array ( [id] => 17492531 [patent_doc_number] => 11281836 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-22 [patent_title] => Cell structures and semiconductor devices having same [patent_app_type] => utility [patent_app_number] => 17/222021 [patent_app_country] => US [patent_app_date] => 2021-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 23 [patent_no_of_words] => 15393 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17222021 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/222021
Cell structures and semiconductor devices having same Apr 4, 2021 Issued
Array ( [id] => 17847025 [patent_doc_number] => 11436402 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-09-06 [patent_title] => Electronic design 3D mixed placement and unfolding [patent_app_type] => utility [patent_app_number] => 17/219695 [patent_app_country] => US [patent_app_date] => 2021-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 5289 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17219695 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/219695
Electronic design 3D mixed placement and unfolding Mar 30, 2021 Issued
Array ( [id] => 17091991 [patent_doc_number] => 11120181 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-09-14 [patent_title] => Structural joint damage detector tool [patent_app_type] => utility [patent_app_number] => 17/213663 [patent_app_country] => US [patent_app_date] => 2021-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9628 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 253 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17213663 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/213663
Structural joint damage detector tool Mar 25, 2021 Issued
Array ( [id] => 17824829 [patent_doc_number] => 11429777 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-30 [patent_title] => Methods of estimating warpage of interposers and methods of manufacturing semiconductor package by using the same [patent_app_type] => utility [patent_app_number] => 17/213538 [patent_app_country] => US [patent_app_date] => 2021-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8467 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17213538 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/213538
Methods of estimating warpage of interposers and methods of manufacturing semiconductor package by using the same Mar 25, 2021 Issued
Array ( [id] => 17824827 [patent_doc_number] => 11429775 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-08-30 [patent_title] => Automatic generation of sub-cells for an analog integrated circuit [patent_app_type] => utility [patent_app_number] => 17/212499 [patent_app_country] => US [patent_app_date] => 2021-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 24 [patent_no_of_words] => 8486 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17212499 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/212499
Automatic generation of sub-cells for an analog integrated circuit Mar 24, 2021 Issued
Array ( [id] => 16994544 [patent_doc_number] => 20210232964 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-29 [patent_title] => Method and Apparatus for Evaluating Quantum Gate in Superconducting Circuit, Device and Storage Medium [patent_app_type] => utility [patent_app_number] => 17/210950 [patent_app_country] => US [patent_app_date] => 2021-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8514 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17210950 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/210950
Method and Apparatus for Evaluating Quantum Gate in Superconducting Circuit, Device and Storage Medium Mar 23, 2021 Abandoned
Array ( [id] => 17899563 [patent_doc_number] => 20220309225 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-29 [patent_title] => Metal Routing Techniques [patent_app_type] => utility [patent_app_number] => 17/209903 [patent_app_country] => US [patent_app_date] => 2021-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7961 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17209903 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/209903
Metal routing techniques Mar 22, 2021 Issued
Array ( [id] => 16935041 [patent_doc_number] => 20210200930 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-01 [patent_title] => METHOD FOR EVALUATING FAILURE-IN-TIME [patent_app_type] => utility [patent_app_number] => 17/204275 [patent_app_country] => US [patent_app_date] => 2021-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5287 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17204275 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/204275
Method for evaluating failure-in-time Mar 16, 2021 Issued
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