
Eric D. Lee
Examiner (ID: 1963, Phone: (571)270-7098 , Office: P/2851 )
| Most Active Art Unit | 2851 |
| Art Unit(s) | 2851, 2825 |
| Total Applications | 773 |
| Issued Applications | 618 |
| Pending Applications | 46 |
| Abandoned Applications | 125 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 17778966
[patent_doc_number] => 20220245316
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-08-04
[patent_title] => COMPUTER-IMPLEMENTED METHOD OF PERFORMING VOLTAGE RULE CHECK IN AN ELECTRONIC DESIGN AUTOMATION PLATFORM
[patent_app_type] => utility
[patent_app_number] => 17/373790
[patent_app_country] => US
[patent_app_date] => 2021-07-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5224
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -10
[patent_words_short_claim] => 124
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17373790
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/373790 | Computer-implemented method of performing voltage rule check in an electronic design automation platform | Jul 12, 2021 | Issued |
Array
(
[id] => 18047010
[patent_doc_number] => 11520966
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-12-06
[patent_title] => Automated assisted circuit validation
[patent_app_type] => utility
[patent_app_number] => 17/370976
[patent_app_country] => US
[patent_app_date] => 2021-07-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 6
[patent_no_of_words] => 7066
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 206
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17370976
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/370976 | Automated assisted circuit validation | Jul 7, 2021 | Issued |
Array
(
[id] => 19212856
[patent_doc_number] => 12001919
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2024-06-04
[patent_title] => Frequency selective photon dissipation for an energy gap protected qubit
[patent_app_type] => utility
[patent_app_number] => 17/364813
[patent_app_country] => US
[patent_app_date] => 2021-06-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 10
[patent_no_of_words] => 8120
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 113
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17364813
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/364813 | Frequency selective photon dissipation for an energy gap protected qubit | Jun 29, 2021 | Issued |
Array
(
[id] => 17172830
[patent_doc_number] => 20210326500
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-10-21
[patent_title] => GENERATION OF DYNAMIC DESIGN FLOWS FOR INTEGRATED CIRCUITS
[patent_app_type] => utility
[patent_app_number] => 17/361253
[patent_app_country] => US
[patent_app_date] => 2021-06-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 26916
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 110
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17361253
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/361253 | Generation of dynamic design flows for integrated circuits | Jun 27, 2021 | Issued |
Array
(
[id] => 18262334
[patent_doc_number] => 11610036
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-03-21
[patent_title] => Integrated circuits as a service
[patent_app_type] => utility
[patent_app_number] => 17/361238
[patent_app_country] => US
[patent_app_date] => 2021-06-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 19138
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 131
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17361238
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/361238 | Integrated circuits as a service | Jun 27, 2021 | Issued |
Array
(
[id] => 17622254
[patent_doc_number] => 11341311
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2022-05-24
[patent_title] => Generation and selection of universally routable via mesh specifications in an integrated circuit
[patent_app_type] => utility
[patent_app_number] => 17/356709
[patent_app_country] => US
[patent_app_date] => 2021-06-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 10
[patent_no_of_words] => 7732
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 181
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17356709
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/356709 | Generation and selection of universally routable via mesh specifications in an integrated circuit | Jun 23, 2021 | Issued |
Array
(
[id] => 18316855
[patent_doc_number] => 11630937
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-04-18
[patent_title] => System and method for predictive 3-D virtual fabrication
[patent_app_type] => utility
[patent_app_number] => 17/355533
[patent_app_country] => US
[patent_app_date] => 2021-06-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 28
[patent_figures_cnt] => 43
[patent_no_of_words] => 13758
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 255
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17355533
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/355533 | System and method for predictive 3-D virtual fabrication | Jun 22, 2021 | Issued |
Array
(
[id] => 18279053
[patent_doc_number] => 20230094525
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-03-30
[patent_title] => CIRCUIT BOARD ASSEMBLY MANUFACTURING METHOD, CIRCUIT BOARD ASSEMBLY MANUFACTURED BY SAME, AND ELECTRIC VEHICLE INCLUDING SAME
[patent_app_type] => utility
[patent_app_number] => 17/800775
[patent_app_country] => US
[patent_app_date] => 2021-06-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8369
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -15
[patent_words_short_claim] => 99
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17800775
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/800775 | CIRCUIT BOARD ASSEMBLY MANUFACTURING METHOD, CIRCUIT BOARD ASSEMBLY MANUFACTURED BY SAME, AND ELECTRIC VEHICLE INCLUDING SAME | Jun 14, 2021 | Pending |
Array
(
[id] => 19828064
[patent_doc_number] => 12248848
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-03-11
[patent_title] => Scalable gate control in quantum circuit assemblies
[patent_app_type] => utility
[patent_app_number] => 17/340173
[patent_app_country] => US
[patent_app_date] => 2021-06-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 31
[patent_figures_cnt] => 45
[patent_no_of_words] => 31864
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 92
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17340173
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/340173 | Scalable gate control in quantum circuit assemblies | Jun 6, 2021 | Issued |
Array
(
[id] => 17637191
[patent_doc_number] => 11347915
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2022-05-31
[patent_title] => System and method for objective probing and generation of timing constraints associated with an electronic circuit design
[patent_app_type] => utility
[patent_app_number] => 17/338033
[patent_app_country] => US
[patent_app_date] => 2021-06-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 5918
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 78
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17338033
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/338033 | System and method for objective probing and generation of timing constraints associated with an electronic circuit design | Jun 2, 2021 | Issued |
Array
(
[id] => 18038954
[patent_doc_number] => 20220383170
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-12-01
[patent_title] => SYNCHRONIZING OPERATION OF CONTROL CIRCUITS IN A QUANTUM CIRCUIT ASSEMBLY
[patent_app_type] => utility
[patent_app_number] => 17/332182
[patent_app_country] => US
[patent_app_date] => 2021-05-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 25628
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 67
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17332182
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/332182 | SYNCHRONIZING OPERATION OF CONTROL CIRCUITS IN A QUANTUM CIRCUIT ASSEMBLY | May 26, 2021 | Abandoned |
Array
(
[id] => 17247387
[patent_doc_number] => 20210367132
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-11-25
[patent_title] => DRIVING CIRCUIT AND DRIVING METHOD
[patent_app_type] => utility
[patent_app_number] => 17/325922
[patent_app_country] => US
[patent_app_date] => 2021-05-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 14300
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 129
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17325922
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/325922 | Driving circuit and driving method | May 19, 2021 | Issued |
Array
(
[id] => 17528917
[patent_doc_number] => 11301606
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2022-04-12
[patent_title] => Counting method for counting the stage number passing through a signal path on a graphical user interface
[patent_app_type] => utility
[patent_app_number] => 17/317009
[patent_app_country] => US
[patent_app_date] => 2021-05-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 4043
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 143
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17317009
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/317009 | Counting method for counting the stage number passing through a signal path on a graphical user interface | May 10, 2021 | Issued |
Array
(
[id] => 17024429
[patent_doc_number] => 20210248301
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-08-12
[patent_title] => PUZZLE-BASED PATTERN ANALYSIS AND CLASSIFICATION
[patent_app_type] => utility
[patent_app_number] => 17/245834
[patent_app_country] => US
[patent_app_date] => 2021-04-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12642
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -8
[patent_words_short_claim] => 169
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17245834
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/245834 | Puzzle-based pattern analysis and classification | Apr 29, 2021 | Issued |
Array
(
[id] => 17771504
[patent_doc_number] => 11403447
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2022-08-02
[patent_title] => Runtime intellectual property core metadata to rebuild a next-compile-time intellectual property core
[patent_app_type] => utility
[patent_app_number] => 17/243730
[patent_app_country] => US
[patent_app_date] => 2021-04-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 10056
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 148
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17243730
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/243730 | Runtime intellectual property core metadata to rebuild a next-compile-time intellectual property core | Apr 28, 2021 | Issued |
Array
(
[id] => 18119584
[patent_doc_number] => 11550979
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-01-10
[patent_title] => Implementing and verifying safety measures in a system design based on safety specification generated from safety requirements
[patent_app_type] => utility
[patent_app_number] => 17/235802
[patent_app_country] => US
[patent_app_date] => 2021-04-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 8252
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 152
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17235802
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/235802 | Implementing and verifying safety measures in a system design based on safety specification generated from safety requirements | Apr 19, 2021 | Issued |
Array
(
[id] => 19740143
[patent_doc_number] => 12216978
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-02-04
[patent_title] => Routing structure of semiconductor device and forming method thereof
[patent_app_type] => utility
[patent_app_number] => 17/225903
[patent_app_country] => US
[patent_app_date] => 2021-04-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 11076
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 283
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17225903
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/225903 | Routing structure of semiconductor device and forming method thereof | Apr 7, 2021 | Issued |
Array
(
[id] => 19259906
[patent_doc_number] => 12019965
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-06-25
[patent_title] => Integrated circuit including standard cell and method of manufacturing the integrated circuit
[patent_app_type] => utility
[patent_app_number] => 17/225773
[patent_app_country] => US
[patent_app_date] => 2021-04-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 8237
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 192
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17225773
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/225773 | Integrated circuit including standard cell and method of manufacturing the integrated circuit | Apr 7, 2021 | Issued |
Array
(
[id] => 18155145
[patent_doc_number] => 11568126
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-01-31
[patent_title] => Integrated circuit device design method and system
[patent_app_type] => utility
[patent_app_number] => 17/223612
[patent_app_country] => US
[patent_app_date] => 2021-04-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 7894
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 149
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17223612
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/223612 | Integrated circuit device design method and system | Apr 5, 2021 | Issued |
Array
(
[id] => 17492531
[patent_doc_number] => 11281836
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-03-22
[patent_title] => Cell structures and semiconductor devices having same
[patent_app_type] => utility
[patent_app_number] => 17/222021
[patent_app_country] => US
[patent_app_date] => 2021-04-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 23
[patent_no_of_words] => 15393
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 184
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17222021
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/222021 | Cell structures and semiconductor devices having same | Apr 4, 2021 | Issued |