
Eric E. Silverman
Examiner (ID: 15411)
| Most Active Art Unit | 1618 |
| Art Unit(s) | 1618, 1615 |
| Total Applications | 298 |
| Issued Applications | 111 |
| Pending Applications | 2 |
| Abandoned Applications | 185 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 1086408
[patent_doc_number] => 06831294
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-12-14
[patent_title] => 'Semiconductor integrated circuit device having bump electrodes for signal or power only, and testing pads that are not coupled to bump electrodes'
[patent_app_type] => B1
[patent_app_number] => 09/869274
[patent_app_country] => US
[patent_app_date] => 2001-06-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 38
[patent_figures_cnt] => 59
[patent_no_of_words] => 28929
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 82
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/831/06831294.pdf
[firstpage_image] =>[orig_patent_app_number] => 09869274
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/869274 | Semiconductor integrated circuit device having bump electrodes for signal or power only, and testing pads that are not coupled to bump electrodes | Jun 25, 2001 | Issued |
Array
(
[id] => 1034489
[patent_doc_number] => 06875698
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-04-05
[patent_title] => 'Dry etching method'
[patent_app_type] => utility
[patent_app_number] => 09/892023
[patent_app_country] => US
[patent_app_date] => 2001-06-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 1638
[patent_no_of_claims] => 21
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[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/875/06875698.pdf
[firstpage_image] =>[orig_patent_app_number] => 09892023
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/892023 | Dry etching method | Jun 25, 2001 | Issued |
Array
(
[id] => 1400449
[patent_doc_number] => 06545366
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-04-08
[patent_title] => 'Multiple chip package semiconductor device'
[patent_app_type] => B2
[patent_app_number] => 09/887164
[patent_app_country] => US
[patent_app_date] => 2001-06-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 19
[patent_no_of_words] => 6933
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[patent_words_short_claim] => 196
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/545/06545366.pdf
[firstpage_image] =>[orig_patent_app_number] => 09887164
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/887164 | Multiple chip package semiconductor device | Jun 24, 2001 | Issued |
Array
(
[id] => 1270367
[patent_doc_number] => 06653235
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-11-25
[patent_title] => 'Fabricating process for forming multi-layered metal bumps by electroless plating'
[patent_app_type] => B2
[patent_app_number] => 09/887074
[patent_app_country] => US
[patent_app_date] => 2001-06-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 15
[patent_no_of_words] => 2330
[patent_no_of_claims] => 17
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/653/06653235.pdf
[firstpage_image] =>[orig_patent_app_number] => 09887074
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/887074 | Fabricating process for forming multi-layered metal bumps by electroless plating | Jun 24, 2001 | Issued |
Array
(
[id] => 1327410
[patent_doc_number] => 06599844
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-07-29
[patent_title] => 'Method and forming fine patterns of semiconductor devices using passivation layers'
[patent_app_type] => B2
[patent_app_number] => 09/886463
[patent_app_country] => US
[patent_app_date] => 2001-06-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[pdf_file] => patents/06/599/06599844.pdf
[firstpage_image] =>[orig_patent_app_number] => 09886463
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/886463 | Method and forming fine patterns of semiconductor devices using passivation layers | Jun 21, 2001 | Issued |
Array
(
[id] => 1253310
[patent_doc_number] => 06670234
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-12-30
[patent_title] => 'Method of integrating volatile and non-volatile memory cells on the same substrate and a semiconductor memory device thereof'
[patent_app_type] => B2
[patent_app_number] => 09/887403
[patent_app_country] => US
[patent_app_date] => 2001-06-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
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[pdf_file] => patents/06/670/06670234.pdf
[firstpage_image] =>[orig_patent_app_number] => 09887403
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/887403 | Method of integrating volatile and non-volatile memory cells on the same substrate and a semiconductor memory device thereof | Jun 21, 2001 | Issued |
Array
(
[id] => 1312159
[patent_doc_number] => 06610573
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-08-26
[patent_title] => 'Method for forming a single wiring level for transistors with planar and vertical gates on the same substrate'
[patent_app_type] => B2
[patent_app_number] => 09/888193
[patent_app_country] => US
[patent_app_date] => 2001-06-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 16
[patent_no_of_words] => 3785
[patent_no_of_claims] => 15
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/610/06610573.pdf
[firstpage_image] =>[orig_patent_app_number] => 09888193
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/888193 | Method for forming a single wiring level for transistors with planar and vertical gates on the same substrate | Jun 21, 2001 | Issued |
Array
(
[id] => 6327171
[patent_doc_number] => 20020197763
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-12-26
[patent_title] => 'Method of forming a color filter'
[patent_app_type] => new
[patent_app_number] => 09/885044
[patent_app_country] => US
[patent_app_date] => 2001-06-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 2514
[patent_no_of_claims] => 17
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[pdf_file] => publications/A1/0197/20020197763.pdf
[firstpage_image] =>[orig_patent_app_number] => 09885044
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/885044 | Method of forming a color filter | Jun 20, 2001 | Issued |
Array
(
[id] => 6327461
[patent_doc_number] => 20020197842
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-12-26
[patent_title] => ' Bumping process'
[patent_app_type] => new
[patent_app_number] => 09/886834
[patent_app_country] => US
[patent_app_date] => 2001-06-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[pdf_file] => publications/A1/0197/20020197842.pdf
[firstpage_image] =>[orig_patent_app_number] => 09886834
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/886834 | Bumping process | Jun 20, 2001 | Issued |
Array
(
[id] => 1354787
[patent_doc_number] => 06576542
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-06-10
[patent_title] => 'Conductive lines, coaxial lines, integrated circuitry, and methods of forming conductive lines, coaxial lines, and integrated circuitry'
[patent_app_type] => B2
[patent_app_number] => 09/887085
[patent_app_country] => US
[patent_app_date] => 2001-06-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[patent_no_of_words] => 2083
[patent_no_of_claims] => 45
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[pdf_file] => patents/06/576/06576542.pdf
[firstpage_image] =>[orig_patent_app_number] => 09887085
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/887085 | Conductive lines, coaxial lines, integrated circuitry, and methods of forming conductive lines, coaxial lines, and integrated circuitry | Jun 20, 2001 | Issued |
Array
(
[id] => 6317178
[patent_doc_number] => 20020195707
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-12-26
[patent_title] => 'Extension of fatigue life for C4 solder ball to chip connection'
[patent_app_type] => new
[patent_app_number] => 09/885853
[patent_app_country] => US
[patent_app_date] => 2001-06-20
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0195/20020195707.pdf
[firstpage_image] =>[orig_patent_app_number] => 09885853
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/885853 | Extension of fatigue life for C4 solder ball to chip connection | Jun 19, 2001 | Issued |
Array
(
[id] => 1297455
[patent_doc_number] => 06627523
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-09-30
[patent_title] => 'Method of forming a metal wiring in a semiconductor device'
[patent_app_type] => B2
[patent_app_number] => 09/883964
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[pdf_file] => patents/06/627/06627523.pdf
[firstpage_image] =>[orig_patent_app_number] => 09883964
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/883964 | Method of forming a metal wiring in a semiconductor device | Jun 19, 2001 | Issued |
Array
(
[id] => 956178
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[patent_issue_date] => 2005-10-18
[patent_title] => 'Closed loop residual gas analyzer process control technique'
[patent_app_type] => utility
[patent_app_number] => 09/883883
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[firstpage_image] =>[orig_patent_app_number] => 09883883
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/883883 | Closed loop residual gas analyzer process control technique | Jun 17, 2001 | Issued |
Array
(
[id] => 1197703
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[patent_issue_date] => 2004-04-27
[patent_title] => 'Vertical color filter detector group and array'
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[patent_app_number] => 09/884863
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[firstpage_image] =>[orig_patent_app_number] => 09884863
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/884863 | Vertical color filter detector group and array | Jun 17, 2001 | Issued |
Array
(
[id] => 1385609
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[patent_issue_date] => 2003-04-15
[patent_title] => 'Method of forming a storage node contact hole in a porous insulator layer'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/883164 | Method of forming a storage node contact hole in a porous insulator layer | Jun 17, 2001 | Issued |
Array
(
[id] => 6493396
[patent_doc_number] => 20020190232
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[patent_issue_date] => 2002-12-19
[patent_title] => 'Structure and method for fabricating semiconductor structures and devices for detecting smoke'
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[patent_app_number] => 09/882067
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[firstpage_image] =>[orig_patent_app_number] => 09882067
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/882067 | Structure and method for fabricating semiconductor structures and devices for detecting smoke | Jun 17, 2001 | Abandoned |
Array
(
[id] => 6921579
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[patent_title] => 'Method and apparatus for separating semiconductor elements, and mounting method of semiconductor elements'
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Array
(
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[patent_title] => 'Semiconductor device having cobalt silicide film in which diffusion of cobalt atoms is inhibited and its production process'
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Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/876733 | Heat sink sheet and fabrication method therefor | Jun 6, 2001 | Issued |
Array
(
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[patent_title] => 'Method of making electronic materials'
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[firstpage_image] =>[orig_patent_app_number] => 09875115
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/875115 | Method of making electronic materials | Jun 5, 2001 | Issued |