Eric E. Silverman

Array ( [id] => 6404618 [patent_doc_number] => 20020037481 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-03-28 [patent_title] => 'Method of and apparatus for substrate pre-treatment' [patent_app_type] => new [patent_app_number] => 09/874330 [patent_app_country] => US [patent_app_date] => 2001-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 13711 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0037/20020037481.pdf [firstpage_image] =>[orig_patent_app_number] => 09874330 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6399863 [patent_doc_number] => 20020181827 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-05 [patent_title] => 'Optically-communicating integrated circuits' [patent_app_type] => new [patent_app_number] => 09/870836 [patent_app_country] => US [patent_app_date] => 2001-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 15916 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0181/20020181827.pdf [firstpage_image] =>[orig_patent_app_number] => 09870836 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1371817 [patent_doc_number] => 06562700 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-13 [patent_title] => 'Process for removal of resist mask over low k carbon-doped silicon oxide dielectric material of an integrated circuit structure, and removal of residues from via etch and resist mask removal' [patent_app_type] => B1 [patent_app_number] => 09/873043 [patent_app_country] => US [patent_app_date] => 2001-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 4101 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/562/06562700.pdf [firstpage_image] =>[orig_patent_app_number] => 09873043 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1174836 [patent_doc_number] => 06746880 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-06-08 [patent_title] => 'Method for making electrical contact with a rear side of a semiconductor substrate during its processing' [patent_app_type] => B2 [patent_app_number] => 09/871013 [patent_app_country] => US [patent_app_date] => 2001-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3571 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 271 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/746/06746880.pdf [firstpage_image] =>[orig_patent_app_number] => 09871013 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6141736 [patent_doc_number] => 20020001889 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-03 [patent_title] => 'Methods for forming conductive contact body for integrated circuits using dummy dielectric layer' [patent_app_type] => new [patent_app_number] => 09/866323 [patent_app_country] => US [patent_app_date] => 2001-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8964 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0001/20020001889.pdf [firstpage_image] =>[orig_patent_app_number] => 09866323 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7625530 [patent_doc_number] => 06723639 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-04-20 [patent_title] => 'Prevention of post CMP defects in Cu/FSG process' [patent_app_type] => B1 [patent_app_number] => 09/863223 [patent_app_country] => US [patent_app_date] => 2001-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 1781 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 14 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/723/06723639.pdf [firstpage_image] =>[orig_patent_app_number] => 09863223 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1371028 [patent_doc_number] => 06562646 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-05-13 [patent_title] => 'Method for manufacturing light-emitting device using a group III nitride compound semiconductor' [patent_app_type] => B2 [patent_app_number] => 09/863514 [patent_app_country] => US [patent_app_date] => 2001-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 5444 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/562/06562646.pdf [firstpage_image] =>[orig_patent_app_number] => 09863514 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6447003 [patent_doc_number] => 20020177256 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-11-28 [patent_title] => 'Method of making leadless semiconductor package' [patent_app_type] => new [patent_app_number] => 09/863323 [patent_app_country] => US [patent_app_date] => 2001-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1854 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0177/20020177256.pdf [firstpage_image] =>[orig_patent_app_number] => 09863323 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6141929 [patent_doc_number] => 20020001978 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-03 [patent_title] => 'Method for manufacturing double-faced semiconductor circuits' [patent_app_type] => new [patent_app_number] => 09/863833 [patent_app_country] => US [patent_app_date] => 2001-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3655 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0001/20020001978.pdf [firstpage_image] =>[orig_patent_app_number] => 09863833 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1302421 [patent_doc_number] => 06624486 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-09-23 [patent_title] => 'Method for low topography semiconductor device formation' [patent_app_type] => B2 [patent_app_number] => 09/864033 [patent_app_country] => US [patent_app_date] => 2001-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 2320 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/624/06624486.pdf [firstpage_image] =>[orig_patent_app_number] => 09864033 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1053811 [patent_doc_number] => 06858933 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-02-22 [patent_title] => 'Injection mold for an optical semiconductor package and corresponding optical semiconductor package' [patent_app_type] => utility [patent_app_number] => 09/862984 [patent_app_country] => US [patent_app_date] => 2001-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3302 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/858/06858933.pdf [firstpage_image] =>[orig_patent_app_number] => 09862984 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6111455 [patent_doc_number] => 20020173141 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-11-21 [patent_title] => 'Method for fabricating contact holes in DRAM circuits' [patent_app_type] => new [patent_app_number] => 09/859433 [patent_app_country] => US [patent_app_date] => 2001-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2294 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 237 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0173/20020173141.pdf [firstpage_image] =>[orig_patent_app_number] => 09859433 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6111221 [patent_doc_number] => 20020173059 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-11-21 [patent_title] => 'Method of real-time plasma charging voltage measurement on powered electrode with electrostatic chuck in plasma process chambers' [patent_app_type] => new [patent_app_number] => 09/861033 [patent_app_country] => US [patent_app_date] => 2001-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4307 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0173/20020173059.pdf [firstpage_image] =>[orig_patent_app_number] => 09861033 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1027929 [patent_doc_number] => 06881645 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-04-19 [patent_title] => 'Method of preventing semiconductor layers from bending and semiconductor device formed thereby' [patent_app_type] => utility [patent_app_number] => 09/861443 [patent_app_country] => US [patent_app_date] => 2001-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 18 [patent_no_of_words] => 4068 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/881/06881645.pdf [firstpage_image] =>[orig_patent_app_number] => 09861443 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1119665 [patent_doc_number] => 06797560 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-09-28 [patent_title] => 'Method of manufacturing a capacitor having tantalum oxide film as an insulating film' [patent_app_type] => B2 [patent_app_number] => 09/859513 [patent_app_country] => US [patent_app_date] => 2001-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4212 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 30 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/797/06797560.pdf [firstpage_image] =>[orig_patent_app_number] => 09859513 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6111242 [patent_doc_number] => 20020173075 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-11-21 [patent_title] => 'Method for forming a flip chip semiconductor package, a semiconductor package formed thereby, and a substrate therefor' [patent_app_type] => new [patent_app_number] => 09/860664 [patent_app_country] => US [patent_app_date] => 2001-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4438 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0173/20020173075.pdf [firstpage_image] =>[orig_patent_app_number] => 09860664 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1274052 [patent_doc_number] => 06649517 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-11-18 [patent_title] => 'Copper metal structure for the reduction of intra-metal capacitance' [patent_app_type] => B2 [patent_app_number] => 09/859353 [patent_app_country] => US [patent_app_date] => 2001-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 6438 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 260 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/649/06649517.pdf [firstpage_image] =>[orig_patent_app_number] => 09859353 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6130204 [patent_doc_number] => 20020076924 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-20 [patent_title] => 'Method for forming an electrical interconnection providing improved surface morphololgy of tungsten' [patent_app_type] => new [patent_app_number] => 09/859823 [patent_app_country] => US [patent_app_date] => 2001-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3103 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0076/20020076924.pdf [firstpage_image] =>[orig_patent_app_number] => 09859823 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7634800 [patent_doc_number] => 06656818 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-02 [patent_title] => 'Manufacturing process for semiconductor wafer comprising surface grinding and planarization or polishing' [patent_app_type] => B1 [patent_app_number] => 09/831374 [patent_app_country] => US [patent_app_date] => 2001-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 8638 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 12 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/656/06656818.pdf [firstpage_image] =>[orig_patent_app_number] => 09831374 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 891872 [patent_doc_number] => 07344927 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-03-18 [patent_title] => 'Method and apparatus for manufacturing active matrix device including top gate type TFT' [patent_app_type] => utility [patent_app_number] => 09/681643 [patent_app_country] => US [patent_app_date] => 2001-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3928 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/344/07344927.pdf [firstpage_image] =>[orig_patent_app_number] => 09681643 [rel_patent_id] =>[rel_patent_doc_number] =>)