Search

Eric E. Silverman

Examiner (ID: 15411)

Most Active Art Unit
1618
Art Unit(s)
1618, 1615
Total Applications
298
Issued Applications
111
Pending Applications
2
Abandoned Applications
185

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1248147 [patent_doc_number] => 06673646 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-01-06 [patent_title] => 'Growth of compound semiconductor structures on patterned oxide films and process for fabricating same' [patent_app_type] => B2 [patent_app_number] => 09/795784 [patent_app_country] => US [patent_app_date] => 2001-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 9753 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/673/06673646.pdf [firstpage_image] =>[orig_patent_app_number] => 09795784 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/795784
Growth of compound semiconductor structures on patterned oxide films and process for fabricating same Feb 27, 2001 Issued
Array ( [id] => 1126517 [patent_doc_number] => 06790724 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-09-14 [patent_title] => 'Low leakage one transistor static random access memory' [patent_app_type] => B1 [patent_app_number] => 09/785114 [patent_app_country] => US [patent_app_date] => 2001-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2300 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/790/06790724.pdf [firstpage_image] =>[orig_patent_app_number] => 09785114 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/785114
Low leakage one transistor static random access memory Feb 19, 2001 Issued
Array ( [id] => 1269984 [patent_doc_number] => 06653163 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-11-25 [patent_title] => 'Device for emitting electromagnetic radiation at a predetermined wavelength and a method of producing such device' [patent_app_type] => B2 [patent_app_number] => 09/789954 [patent_app_country] => US [patent_app_date] => 2001-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4971 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/653/06653163.pdf [firstpage_image] =>[orig_patent_app_number] => 09789954 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/789954
Device for emitting electromagnetic radiation at a predetermined wavelength and a method of producing such device Feb 19, 2001 Issued
Array ( [id] => 1318384 [patent_doc_number] => 06605516 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-08-12 [patent_title] => 'Semiconductor wafer, wafer alignment patterns and method of forming wafer alignment patterns' [patent_app_type] => B2 [patent_app_number] => 09/783504 [patent_app_country] => US [patent_app_date] => 2001-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 3995 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/605/06605516.pdf [firstpage_image] =>[orig_patent_app_number] => 09783504 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/783504
Semiconductor wafer, wafer alignment patterns and method of forming wafer alignment patterns Feb 12, 2001 Issued
Array ( [id] => 1324207 [patent_doc_number] => 06602763 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-08-05 [patent_title] => 'Methods of fabricating gallium nitride semiconductor layers by lateral overgrowth' [patent_app_type] => B2 [patent_app_number] => 09/780069 [patent_app_country] => US [patent_app_date] => 2001-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 4272 [patent_no_of_claims] => 64 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/602/06602763.pdf [firstpage_image] =>[orig_patent_app_number] => 09780069 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/780069
Methods of fabricating gallium nitride semiconductor layers by lateral overgrowth Feb 8, 2001 Issued
Array ( [id] => 7078617 [patent_doc_number] => 20010041463 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-15 [patent_title] => 'Electo-optical apparatus and method for fabricating a film, semiconductor device and memory device' [patent_app_type] => new [patent_app_number] => 09/778744 [patent_app_country] => US [patent_app_date] => 2001-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1740 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0041/20010041463.pdf [firstpage_image] =>[orig_patent_app_number] => 09778744 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/778744
Electro-optical apparatus and method for fabricating a film, semiconductor device and memory device at near atmospheric pressure Feb 7, 2001 Issued
Array ( [id] => 1110923 [patent_doc_number] => 06806143 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-10-19 [patent_title] => 'Self-aligned source pocket for flash memory cells' [patent_app_type] => B2 [patent_app_number] => 09/773523 [patent_app_country] => US [patent_app_date] => 2001-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 18 [patent_no_of_words] => 4030 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/806/06806143.pdf [firstpage_image] =>[orig_patent_app_number] => 09773523 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/773523
Self-aligned source pocket for flash memory cells Feb 1, 2001 Issued
Array ( [id] => 1168402 [patent_doc_number] => 06753211 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-06-22 [patent_title] => 'Semiconductor devices and manufacturing methods thereof' [patent_app_type] => B2 [patent_app_number] => 09/774427 [patent_app_country] => US [patent_app_date] => 2001-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 28 [patent_no_of_words] => 11730 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 21 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/753/06753211.pdf [firstpage_image] =>[orig_patent_app_number] => 09774427 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/774427
Semiconductor devices and manufacturing methods thereof Jan 29, 2001 Issued
Array ( [id] => 1536013 [patent_doc_number] => 06337234 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-01-08 [patent_title] => 'Method of fabricating a buried bus coplanar thin film transistor' [patent_app_type] => B2 [patent_app_number] => 09/765664 [patent_app_country] => US [patent_app_date] => 2001-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 23 [patent_no_of_words] => 6494 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/337/06337234.pdf [firstpage_image] =>[orig_patent_app_number] => 09765664 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/765664
Method of fabricating a buried bus coplanar thin film transistor Jan 21, 2001 Issued
Array ( [id] => 1155280 [patent_doc_number] => 06764867 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-07-20 [patent_title] => 'Reticle option layer detection method' [patent_app_type] => B1 [patent_app_number] => 09/764243 [patent_app_country] => US [patent_app_date] => 2001-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 5537 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/764/06764867.pdf [firstpage_image] =>[orig_patent_app_number] => 09764243 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/764243
Reticle option layer detection method Jan 18, 2001 Issued
Array ( [id] => 1104754 [patent_doc_number] => 06812061 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-11-02 [patent_title] => 'Method and apparatus for assembling an array of micro-devices' [patent_app_type] => B1 [patent_app_number] => 09/764913 [patent_app_country] => US [patent_app_date] => 2001-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 19 [patent_no_of_words] => 4368 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/812/06812061.pdf [firstpage_image] =>[orig_patent_app_number] => 09764913 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/764913
Method and apparatus for assembling an array of micro-devices Jan 16, 2001 Issued
Array ( [id] => 7028136 [patent_doc_number] => 20010014495 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-08-16 [patent_title] => 'Method for forming super-steep retrograded channel (SSRC) for cmos transistor using rapid laser annealing to reduce thermal budget' [patent_app_type] => new [patent_app_number] => 09/764632 [patent_app_country] => US [patent_app_date] => 2001-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2077 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0014/20010014495.pdf [firstpage_image] =>[orig_patent_app_number] => 09764632 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/764632
Method for forming super-steep retrograded channel (SSRC) for cmos transistor using rapid laser annealing to reduce thermal budget Jan 16, 2001 Abandoned
Array ( [id] => 6630016 [patent_doc_number] => 20020086472 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-04 [patent_title] => 'Technique to obtain high mobility channels in MOS transistors by forming a strain layer on an underside of a channel' [patent_app_type] => new [patent_app_number] => 09/752333 [patent_app_country] => US [patent_app_date] => 2000-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4110 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 36 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0086/20020086472.pdf [firstpage_image] =>[orig_patent_app_number] => 09752333 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/752333
Technique to obtain high mobility channels in MOS transistors by forming a strain layer on an underside of a channel Dec 28, 2000 Issued
Array ( [id] => 1588603 [patent_doc_number] => 06482657 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-11-19 [patent_title] => 'Methods of manufacturing tunnel magnetoresistive element, thin-film magnetic head and memory element' [patent_app_type] => B2 [patent_app_number] => 09/749563 [patent_app_country] => US [patent_app_date] => 2000-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 25 [patent_no_of_words] => 10034 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/482/06482657.pdf [firstpage_image] =>[orig_patent_app_number] => 09749563 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/749563
Methods of manufacturing tunnel magnetoresistive element, thin-film magnetic head and memory element Dec 27, 2000 Issued
Array ( [id] => 1332370 [patent_doc_number] => 06596605 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-07-22 [patent_title] => 'Method of forming germanium doped polycrystalline silicon gate of MOS transistor and method of forming CMOS transistor device using the same' [patent_app_type] => B2 [patent_app_number] => 09/750943 [patent_app_country] => US [patent_app_date] => 2000-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 3138 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/596/06596605.pdf [firstpage_image] =>[orig_patent_app_number] => 09750943 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/750943
Method of forming germanium doped polycrystalline silicon gate of MOS transistor and method of forming CMOS transistor device using the same Dec 27, 2000 Issued
Array ( [id] => 1335766 [patent_doc_number] => 06593155 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-07-15 [patent_title] => 'Method for determination of cure and oxidation of spin-on dielectric polymers' [patent_app_type] => B2 [patent_app_number] => 09/751484 [patent_app_country] => US [patent_app_date] => 2000-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 4785 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/593/06593155.pdf [firstpage_image] =>[orig_patent_app_number] => 09751484 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/751484
Method for determination of cure and oxidation of spin-on dielectric polymers Dec 27, 2000 Issued
Array ( [id] => 5951508 [patent_doc_number] => 20020006730 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-17 [patent_title] => 'Fine pattern formation method and semiconductor device or liquid crystal device manufacturing method employing this method' [patent_app_type] => new [patent_app_number] => 09/749834 [patent_app_country] => US [patent_app_date] => 2000-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4034 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0006/20020006730.pdf [firstpage_image] =>[orig_patent_app_number] => 09749834 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/749834
Fine pattern formation method and semiconductor device or liquid crystal device manufacturing method employing this method Dec 27, 2000 Issued
Array ( [id] => 7041037 [patent_doc_number] => 20010005624 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-06-28 [patent_title] => 'Semiconductor integrated circuit device and process for manufacturing the same' [patent_app_type] => new-utility [patent_app_number] => 09/748163 [patent_app_country] => US [patent_app_date] => 2000-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 6000 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0005/20010005624.pdf [firstpage_image] =>[orig_patent_app_number] => 09748163 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/748163
Process for multilayer wiring connections and bonding pad adhesion to dielectric in a semiconductor integrated circuit device Dec 26, 2000 Issued
Array ( [id] => 1375013 [patent_doc_number] => 06558964 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-05-06 [patent_title] => 'Method and apparatus for monitoring a semiconductor wafer during a spin drying operation' [patent_app_type] => B2 [patent_app_number] => 09/752614 [patent_app_country] => US [patent_app_date] => 2000-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 4794 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/558/06558964.pdf [firstpage_image] =>[orig_patent_app_number] => 09752614 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/752614
Method and apparatus for monitoring a semiconductor wafer during a spin drying operation Dec 26, 2000 Issued
Array ( [id] => 7041010 [patent_doc_number] => 20010005607 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-06-28 [patent_title] => 'Display unit and method of fabricating the same' [patent_app_type] => new-utility [patent_app_number] => 09/748124 [patent_app_country] => US [patent_app_date] => 2000-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 10079 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0005/20010005607.pdf [firstpage_image] =>[orig_patent_app_number] => 09748124 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/748124
Display unit and method of fabricating the same Dec 26, 2000 Issued
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