Eric E. Silverman

Array ( [id] => 1578034 [patent_doc_number] => 06448118 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-09-10 [patent_title] => 'Semiconductor film manufacturing with selective introduction of crystallization promoting material' [patent_app_type] => B2 [patent_app_number] => 09/749863 [patent_app_country] => US [patent_app_date] => 2000-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 53 [patent_no_of_words] => 7983 [patent_no_of_claims] => 57 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/448/06448118.pdf [firstpage_image] =>[orig_patent_app_number] => 09749863 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1419624 [patent_doc_number] => 06525415 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-02-25 [patent_title] => 'Three-dimensional semiconductor integrated circuit apparatus and manufacturing method therefor' [patent_app_type] => B2 [patent_app_number] => 09/745874 [patent_app_country] => US [patent_app_date] => 2000-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 8192 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/525/06525415.pdf [firstpage_image] =>[orig_patent_app_number] => 09745874 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1393498 [patent_doc_number] => 06541312 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-04-01 [patent_title] => 'Formation of antifuse structure in a three dimensional memory' [patent_app_type] => B2 [patent_app_number] => 09/746083 [patent_app_country] => US [patent_app_date] => 2000-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 37 [patent_no_of_words] => 9870 [patent_no_of_claims] => 58 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 18 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/541/06541312.pdf [firstpage_image] =>[orig_patent_app_number] => 09746083 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1416418 [patent_doc_number] => 06518174 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-02-11 [patent_title] => 'Combined resist strip and barrier etch process for dual damascene structures' [patent_app_type] => B2 [patent_app_number] => 09/746894 [patent_app_country] => US [patent_app_date] => 2000-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 2661 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/518/06518174.pdf [firstpage_image] =>[orig_patent_app_number] => 09746894 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1264419 [patent_doc_number] => 06660593 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-12-09 [patent_title] => 'Method for fabricating oxide layers with different thicknesses' [patent_app_type] => B2 [patent_app_number] => 09/747374 [patent_app_country] => US [patent_app_date] => 2000-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 1400 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/660/06660593.pdf [firstpage_image] =>[orig_patent_app_number] => 09747374 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 553540 [patent_doc_number] => 07160801 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-01-09 [patent_title] => 'Integrated circuit using a dual poly process' [patent_app_type] => utility [patent_app_number] => 09/745780 [patent_app_country] => US [patent_app_date] => 2000-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 19 [patent_no_of_words] => 2655 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 14 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/160/07160801.pdf [firstpage_image] =>[orig_patent_app_number] => 09745780 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1297380 [patent_doc_number] => 06627507 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-09-30 [patent_title] => 'Integrated circuit and method of using porous silicon to achieve component isolation in radio frequency applications' [patent_app_type] => B2 [patent_app_number] => 09/740884 [patent_app_country] => US [patent_app_date] => 2000-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 11 [patent_no_of_words] => 4351 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 31 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/627/06627507.pdf [firstpage_image] =>[orig_patent_app_number] => 09740884 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7000598 [patent_doc_number] => 20010053583 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-12-20 [patent_title] => 'Shallow trench isolation formation process using a sacrificial layer' [patent_app_type] => new [patent_app_number] => 09/745333 [patent_app_country] => US [patent_app_date] => 2000-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2660 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0053/20010053583.pdf [firstpage_image] =>[orig_patent_app_number] => 09745333 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6876682 [patent_doc_number] => 20010006835 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-07-05 [patent_title] => 'Method for manufacturing aluminum oxide film for use in a semiconductor device' [patent_app_type] => new-utility [patent_app_number] => 09/739444 [patent_app_country] => US [patent_app_date] => 2000-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2060 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0006/20010006835.pdf [firstpage_image] =>[orig_patent_app_number] => 09739444 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1327858 [patent_doc_number] => 06603142 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-08-05 [patent_title] => 'Antifuse incorporating tantalum nitride barrier layer' [patent_app_type] => B1 [patent_app_number] => 09/741374 [patent_app_country] => US [patent_app_date] => 2000-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2408 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/603/06603142.pdf [firstpage_image] =>[orig_patent_app_number] => 09741374 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7105365 [patent_doc_number] => 20010004537 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-06-21 [patent_title] => 'Method for fabricating thin film transistors' [patent_app_type] => new-utility [patent_app_number] => 09/737774 [patent_app_country] => US [patent_app_date] => 2000-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2100 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0004/20010004537.pdf [firstpage_image] =>[orig_patent_app_number] => 09737774 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6130144 [patent_doc_number] => 20020076906 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-20 [patent_title] => 'Semiconductor structure including a monocrystalline film, device including the structure, and methods of forming the structure and device' [patent_app_type] => new [patent_app_number] => 09/740268 [patent_app_country] => US [patent_app_date] => 2000-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8810 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 29 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0076/20020076906.pdf [firstpage_image] =>[orig_patent_app_number] => 09740268 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1375344 [patent_doc_number] => 06558987 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-05-06 [patent_title] => 'Thin film transistor and method of fabricating the same' [patent_app_type] => B2 [patent_app_number] => 09/736333 [patent_app_country] => US [patent_app_date] => 2000-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 3275 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/558/06558987.pdf [firstpage_image] =>[orig_patent_app_number] => 09736333 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1428432 [patent_doc_number] => 06504240 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-01-07 [patent_title] => 'Semiconductor device having reliable coupling between wiring substrate and semiconductor pellet' [patent_app_type] => B2 [patent_app_number] => 09/737663 [patent_app_country] => US [patent_app_date] => 2000-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 7908 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/504/06504240.pdf [firstpage_image] =>[orig_patent_app_number] => 09737663 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7014630 [patent_doc_number] => 20010051444 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-12-13 [patent_title] => 'Method for manufacturing aluminum oxide film for use in semiconductor device' [patent_app_type] => new [patent_app_number] => 09/736384 [patent_app_country] => US [patent_app_date] => 2000-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3776 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0051/20010051444.pdf [firstpage_image] =>[orig_patent_app_number] => 09736384 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6130074 [patent_doc_number] => 20020076876 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-20 [patent_title] => 'Method for manufacturing semiconductor devices having ESD protection' [patent_app_type] => new [patent_app_number] => 09/736204 [patent_app_country] => US [patent_app_date] => 2000-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 2537 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0076/20020076876.pdf [firstpage_image] =>[orig_patent_app_number] => 09736204 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6493785 [patent_doc_number] => 20020190273 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-19 [patent_title] => 'Bipolar transistor with upper heterojunction collector and method for making same' [patent_app_type] => new [patent_app_number] => 10/149433 [patent_app_country] => US [patent_app_date] => 2002-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5769 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 30 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0190/20020190273.pdf [firstpage_image] =>[orig_patent_app_number] => 10149433 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6631407 [patent_doc_number] => 20020086548 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-04 [patent_title] => 'Method for forming gate dielectric layer in NROM' [patent_app_type] => new [patent_app_number] => 09/735894 [patent_app_country] => US [patent_app_date] => 2000-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1979 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0086/20020086548.pdf [firstpage_image] =>[orig_patent_app_number] => 09735894 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1416477 [patent_doc_number] => 06509241 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-01-21 [patent_title] => 'Process for fabricating an MOS device having highly-localized halo regions' [patent_app_type] => B2 [patent_app_number] => 09/734754 [patent_app_country] => US [patent_app_date] => 2000-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 4362 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/509/06509241.pdf [firstpage_image] =>[orig_patent_app_number] => 09734754 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6209422 [patent_doc_number] => 20020072228 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-13 [patent_title] => 'Semiconductor conductive pattern formation method' [patent_app_type] => new [patent_app_number] => 09/736043 [patent_app_country] => US [patent_app_date] => 2000-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2801 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0072/20020072228.pdf [firstpage_image] =>[orig_patent_app_number] => 09736043 [rel_patent_id] =>[rel_patent_doc_number] =>)