
Eric E. Silverman
Examiner (ID: 15411)
| Most Active Art Unit | 1618 |
| Art Unit(s) | 1618, 1615 |
| Total Applications | 298 |
| Issued Applications | 111 |
| Pending Applications | 2 |
| Abandoned Applications | 185 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 1372114
[patent_doc_number] => 06562718
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-05-13
[patent_title] => 'Process for forming fully silicided gates'
[patent_app_type] => B1
[patent_app_number] => 09/729700
[patent_app_country] => US
[patent_app_date] => 2000-12-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 9
[patent_no_of_words] => 3006
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 87
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/562/06562718.pdf
[firstpage_image] =>[orig_patent_app_number] => 09729700
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/729700 | Process for forming fully silicided gates | Dec 5, 2000 | Issued |
Array
(
[id] => 1309990
[patent_doc_number] => 06617645
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-09-09
[patent_title] => 'Semiconductor device and manufacturing method thereof'
[patent_app_type] => B2
[patent_app_number] => 09/730417
[patent_app_country] => US
[patent_app_date] => 2000-12-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 45
[patent_no_of_words] => 12565
[patent_no_of_claims] => 65
[patent_no_of_ind_claims] => 10
[patent_words_short_claim] => 55
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/617/06617645.pdf
[firstpage_image] =>[orig_patent_app_number] => 09730417
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/730417 | Semiconductor device and manufacturing method thereof | Dec 3, 2000 | Issued |
Array
(
[id] => 985774
[patent_doc_number] => 06924506
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-08-02
[patent_title] => 'Semiconductor device having channel formation region comprising silicon and containing a group IV element'
[patent_app_type] => utility
[patent_app_number] => 09/726337
[patent_app_country] => US
[patent_app_date] => 2000-12-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 18
[patent_no_of_words] => 8284
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 81
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/924/06924506.pdf
[firstpage_image] =>[orig_patent_app_number] => 09726337
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/726337 | Semiconductor device having channel formation region comprising silicon and containing a group IV element | Nov 30, 2000 | Issued |
Array
(
[id] => 1231324
[patent_doc_number] => 06692998
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-02-17
[patent_title] => 'Integrated high quality diode'
[patent_app_type] => B2
[patent_app_number] => 09/727163
[patent_app_country] => US
[patent_app_date] => 2000-11-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 12
[patent_no_of_words] => 1801
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 255
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/692/06692998.pdf
[firstpage_image] =>[orig_patent_app_number] => 09727163
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/727163 | Integrated high quality diode | Nov 29, 2000 | Issued |
Array
(
[id] => 1361808
[patent_doc_number] => 06569748
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-05-27
[patent_title] => 'Substrate and production method thereof'
[patent_app_type] => B1
[patent_app_number] => 09/706877
[patent_app_country] => US
[patent_app_date] => 2000-11-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 24
[patent_no_of_words] => 14872
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 27
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/569/06569748.pdf
[firstpage_image] =>[orig_patent_app_number] => 09706877
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/706877 | Substrate and production method thereof | Nov 6, 2000 | Issued |
Array
(
[id] => 7623508
[patent_doc_number] => 06686657
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-02-03
[patent_title] => 'Interposer for improved handling of semiconductor wafers and method of use of same'
[patent_app_type] => B1
[patent_app_number] => 09/707873
[patent_app_country] => US
[patent_app_date] => 2000-11-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 14
[patent_no_of_words] => 6131
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 6
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/686/06686657.pdf
[firstpage_image] =>[orig_patent_app_number] => 09707873
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/707873 | Interposer for improved handling of semiconductor wafers and method of use of same | Nov 6, 2000 | Issued |
Array
(
[id] => 1528020
[patent_doc_number] => 06479328
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-11-12
[patent_title] => 'Method of fabricating SOI wafer'
[patent_app_type] => B1
[patent_app_number] => 09/705873
[patent_app_country] => US
[patent_app_date] => 2000-11-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 11
[patent_no_of_words] => 1981
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 236
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/479/06479328.pdf
[firstpage_image] =>[orig_patent_app_number] => 09705873
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/705873 | Method of fabricating SOI wafer | Nov 5, 2000 | Issued |
Array
(
[id] => 1315600
[patent_doc_number] => 06607983
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-08-19
[patent_title] => 'Method of processing a defect source at a wafer edge region in a semiconductor manufacturing'
[patent_app_type] => B1
[patent_app_number] => 09/707353
[patent_app_country] => US
[patent_app_date] => 2000-11-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 4236
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 110
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/607/06607983.pdf
[firstpage_image] =>[orig_patent_app_number] => 09707353
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/707353 | Method of processing a defect source at a wafer edge region in a semiconductor manufacturing | Nov 5, 2000 | Issued |
Array
(
[id] => 1347410
[patent_doc_number] => 06579790
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-06-17
[patent_title] => 'Dual damascene manufacturing process'
[patent_app_type] => B1
[patent_app_number] => 09/707314
[patent_app_country] => US
[patent_app_date] => 2000-11-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 2398
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 125
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/579/06579790.pdf
[firstpage_image] =>[orig_patent_app_number] => 09707314
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/707314 | Dual damascene manufacturing process | Nov 5, 2000 | Issued |
Array
(
[id] => 7631420
[patent_doc_number] => 06635512
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-10-21
[patent_title] => 'Method of producing a semiconductor device by dividing a semiconductor wafer into separate pieces of semiconductor chips'
[patent_app_type] => B1
[patent_app_number] => 09/704563
[patent_app_country] => US
[patent_app_date] => 2000-11-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 16
[patent_no_of_words] => 7940
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 22
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/635/06635512.pdf
[firstpage_image] =>[orig_patent_app_number] => 09704563
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/704563 | Method of producing a semiconductor device by dividing a semiconductor wafer into separate pieces of semiconductor chips | Nov 2, 2000 | Issued |
Array
(
[id] => 1280856
[patent_doc_number] => 06642085
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-11-04
[patent_title] => 'Thin film transistors on plastic substrates with reflective coatings for radiation protection'
[patent_app_type] => B1
[patent_app_number] => 09/705484
[patent_app_country] => US
[patent_app_date] => 2000-11-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 17
[patent_no_of_words] => 4970
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 175
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/642/06642085.pdf
[firstpage_image] =>[orig_patent_app_number] => 09705484
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/705484 | Thin film transistors on plastic substrates with reflective coatings for radiation protection | Nov 2, 2000 | Issued |
Array
(
[id] => 1450079
[patent_doc_number] => 06455422
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-09-24
[patent_title] => 'Densification process hillock suppression method in integrated circuits'
[patent_app_type] => B1
[patent_app_number] => 09/705444
[patent_app_country] => US
[patent_app_date] => 2000-11-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 3192
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 132
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/455/06455422.pdf
[firstpage_image] =>[orig_patent_app_number] => 09705444
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/705444 | Densification process hillock suppression method in integrated circuits | Nov 1, 2000 | Issued |
Array
(
[id] => 7634315
[patent_doc_number] => 06657305
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-12-02
[patent_title] => 'Semiconductor recessed mask interconnect technology'
[patent_app_type] => B1
[patent_app_number] => 09/703734
[patent_app_country] => US
[patent_app_date] => 2000-11-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 2931
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 51
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/657/06657305.pdf
[firstpage_image] =>[orig_patent_app_number] => 09703734
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/703734 | Semiconductor recessed mask interconnect technology | Oct 31, 2000 | Issued |
Array
(
[id] => 1371319
[patent_doc_number] => 06562666
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-05-13
[patent_title] => 'Integrated circuits with reduced substrate capacitance'
[patent_app_type] => B1
[patent_app_number] => 09/702314
[patent_app_country] => US
[patent_app_date] => 2000-10-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 2761
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 58
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/562/06562666.pdf
[firstpage_image] =>[orig_patent_app_number] => 09702314
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/702314 | Integrated circuits with reduced substrate capacitance | Oct 30, 2000 | Issued |
| 09/702563 | Semiconductor package and method for making the same | Oct 30, 2000 | Abandoned |
Array
(
[id] => 1418734
[patent_doc_number] => 06514877
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-02-04
[patent_title] => 'Method using sub-micron silicide structures formed by direct-write electron beam lithography for fabricating masks for extreme ultra-violet and deep ultra-violet lithography'
[patent_app_type] => B1
[patent_app_number] => 09/697403
[patent_app_country] => US
[patent_app_date] => 2000-10-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 12
[patent_no_of_words] => 3360
[patent_no_of_claims] => 3
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[patent_words_short_claim] => 304
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/514/06514877.pdf
[firstpage_image] =>[orig_patent_app_number] => 09697403
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/697403 | Method using sub-micron silicide structures formed by direct-write electron beam lithography for fabricating masks for extreme ultra-violet and deep ultra-violet lithography | Oct 26, 2000 | Issued |
Array
(
[id] => 1297569
[patent_doc_number] => 06627541
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-09-30
[patent_title] => 'Reflow method for construction of conductive vias'
[patent_app_type] => B1
[patent_app_number] => 09/697923
[patent_app_country] => US
[patent_app_date] => 2000-10-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 4
[patent_no_of_words] => 1740
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 119
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/627/06627541.pdf
[firstpage_image] =>[orig_patent_app_number] => 09697923
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/697923 | Reflow method for construction of conductive vias | Oct 25, 2000 | Issued |
| 09/695764 | FABRICATION OF ON-PACKAGE AND ON-CHIP STRUCTURE USING BUILD-UP LAYER PROCESS | Oct 23, 2000 | Abandoned |
Array
(
[id] => 1382095
[patent_doc_number] => 06551905
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-04-22
[patent_title] => 'Wafer adhesive for semiconductor dry etch applications'
[patent_app_type] => B1
[patent_app_number] => 09/693716
[patent_app_country] => US
[patent_app_date] => 2000-10-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 2029
[patent_no_of_claims] => 20
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/551/06551905.pdf
[firstpage_image] =>[orig_patent_app_number] => 09693716
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/693716 | Wafer adhesive for semiconductor dry etch applications | Oct 19, 2000 | Issued |
Array
(
[id] => 1389096
[patent_doc_number] => 06544802
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-04-08
[patent_title] => 'Wafer inspection system and method for selectively inspecting conductive pattern defects'
[patent_app_type] => B1
[patent_app_number] => 09/685094
[patent_app_country] => US
[patent_app_date] => 2000-10-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/544/06544802.pdf
[firstpage_image] =>[orig_patent_app_number] => 09685094
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/685094 | Wafer inspection system and method for selectively inspecting conductive pattern defects | Oct 10, 2000 | Issued |