Eric E. Silverman

Array ( [id] => 1361821 [patent_doc_number] => 06569749 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-27 [patent_title] => 'Silicon and oxygen ion co-implanation for metallic gettering in epitaxial wafers' [patent_app_type] => B1 [patent_app_number] => 09/407868 [patent_app_country] => US [patent_app_date] => 1999-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4074 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/569/06569749.pdf [firstpage_image] =>[orig_patent_app_number] => 09407868 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1375378 [patent_doc_number] => 06558989 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-06 [patent_title] => 'Method for crystallizing silicon film and thin film transistor and fabricating method using the same' [patent_app_type] => B1 [patent_app_number] => 09/401924 [patent_app_country] => US [patent_app_date] => 1999-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 15 [patent_no_of_words] => 3609 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/558/06558989.pdf [firstpage_image] =>[orig_patent_app_number] => 09401924 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1571244 [patent_doc_number] => 06498399 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-12-24 [patent_title] => 'Low dielectric-constant dielectric for etchstop in dual damascene backend of integrated circuits' [patent_app_type] => B2 [patent_app_number] => 09/391721 [patent_app_country] => US [patent_app_date] => 1999-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 6768 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/498/06498399.pdf [firstpage_image] =>[orig_patent_app_number] => 09391721 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1553441 [patent_doc_number] => 06348369 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-19 [patent_title] => 'Method for manufacturing semiconductor devices' [patent_app_type] => B1 [patent_app_number] => 09/390513 [patent_app_country] => US [patent_app_date] => 1999-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 10739 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/348/06348369.pdf [firstpage_image] =>[orig_patent_app_number] => 09390513 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4368736 [patent_doc_number] => 06287919 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-11 [patent_title] => 'Integrated circuit memory cell having a small active area and method of forming same' [patent_app_type] => 1 [patent_app_number] => 9/372893 [patent_app_country] => US [patent_app_date] => 1999-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 3891 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/287/06287919.pdf [firstpage_image] =>[orig_patent_app_number] => 372893 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4350462 [patent_doc_number] => 06291307 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-18 [patent_title] => 'Method and structure to make planar analog capacitor on the top of a STI structure' [patent_app_type] => 1 [patent_app_number] => 9/368863 [patent_app_country] => US [patent_app_date] => 1999-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 5489 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/291/06291307.pdf [firstpage_image] =>[orig_patent_app_number] => 368863 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4373697 [patent_doc_number] => 06274940 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-14 [patent_title] => 'Semiconductor wafer, a chemical-mechanical alignment mark, and an apparatus for improving alignment for metal masking in conjunction with oxide and tungsten CMP' [patent_app_type] => 1 [patent_app_number] => 9/360783 [patent_app_country] => US [patent_app_date] => 1999-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 4262 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/274/06274940.pdf [firstpage_image] =>[orig_patent_app_number] => 360783 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4408125 [patent_doc_number] => 06265259 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-24 [patent_title] => 'Method to fabricate deep sub-.mu.m CMOSFETs' [patent_app_type] => 1 [patent_app_number] => 9/351876 [patent_app_country] => US [patent_app_date] => 1999-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2381 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/265/06265259.pdf [firstpage_image] =>[orig_patent_app_number] => 351876 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4271178 [patent_doc_number] => 06323094 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-27 [patent_title] => 'Method to fabricate deep sub-.mu.m CMOSFETs' [patent_app_type] => 1 [patent_app_number] => 9/345925 [patent_app_country] => US [patent_app_date] => 1999-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 3439 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/323/06323094.pdf [firstpage_image] =>[orig_patent_app_number] => 345925 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4404506 [patent_doc_number] => 06271072 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-07 [patent_title] => 'Method of manufacturing a storage node having five polysilicon bars' [patent_app_type] => 1 [patent_app_number] => 9/332424 [patent_app_country] => US [patent_app_date] => 1999-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 2674 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 466 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/271/06271072.pdf [firstpage_image] =>[orig_patent_app_number] => 332424 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 790817 [patent_doc_number] => 06984840 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-01-10 [patent_title] => 'Optical semiconductor device having an epitaxial layer of III-V compound semiconductor material containing N as a group V element' [patent_app_type] => utility [patent_app_number] => 09/313764 [patent_app_country] => US [patent_app_date] => 1999-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 28 [patent_no_of_words] => 14277 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/984/06984840.pdf [firstpage_image] =>[orig_patent_app_number] => 09313764 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4324999 [patent_doc_number] => 06329265 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-11 [patent_title] => 'Method of making a semiconductor device using processing from both sides of a workpiece' [patent_app_type] => 1 [patent_app_number] => 9/305486 [patent_app_country] => US [patent_app_date] => 1999-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 89 [patent_no_of_words] => 14134 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/329/06329265.pdf [firstpage_image] =>[orig_patent_app_number] => 305486 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1435898 [patent_doc_number] => 06355541 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-12 [patent_title] => 'Method for transfer of thin-film of silicon carbide via implantation and wafer bonding' [patent_app_type] => B1 [patent_app_number] => 09/296143 [patent_app_country] => US [patent_app_date] => 1999-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 3925 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/355/06355541.pdf [firstpage_image] =>[orig_patent_app_number] => 09296143 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1376711 [patent_doc_number] => 06559075 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-06 [patent_title] => 'Method of separating two layers of material from one another and electronic components produced using this process' [patent_app_type] => B1 [patent_app_number] => 09/283907 [patent_app_country] => US [patent_app_date] => 1999-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 4964 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/559/06559075.pdf [firstpage_image] =>[orig_patent_app_number] => 09283907 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1089098 [patent_doc_number] => 06828190 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-12-07 [patent_title] => 'Method for manufacturing capacitor of semiconductor device having dielectric layer of high dielectric constant' [patent_app_type] => B2 [patent_app_number] => 09/276803 [patent_app_country] => US [patent_app_date] => 1999-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 5141 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/828/06828190.pdf [firstpage_image] =>[orig_patent_app_number] => 09276803 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 519287 [patent_doc_number] => 07193246 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-03-20 [patent_title] => 'Nitride semiconductor device' [patent_app_type] => utility [patent_app_number] => 09/265579 [patent_app_country] => US [patent_app_date] => 1999-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 47922 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 25 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/193/07193246.pdf [firstpage_image] =>[orig_patent_app_number] => 09265579 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1435879 [patent_doc_number] => 06355522 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-12 [patent_title] => 'Effect of doped amorphous Si thickness on better poly 1 contact resistance performance for nand type flash memory devices' [patent_app_type] => B1 [patent_app_number] => 09/263699 [patent_app_country] => US [patent_app_date] => 1999-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 6304 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/355/06355522.pdf [firstpage_image] =>[orig_patent_app_number] => 09263699 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7028237 [patent_doc_number] => 20010014527 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-08-16 [patent_title] => 'METHOD AND SYSTEM FOR PROVIDING ELECTRICAL INSULATION FOR LOCAL INTERCONNECT IN A LOGIC CIRCUIT' [patent_app_type] => new [patent_app_number] => 09/262130 [patent_app_country] => US [patent_app_date] => 1999-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2125 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0014/20010014527.pdf [firstpage_image] =>[orig_patent_app_number] => 09262130 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4300920 [patent_doc_number] => 06184548 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-06 [patent_title] => 'DRAM cell and array to store two-bit data having merged stack capacitor and trench capacitor' [patent_app_type] => 1 [patent_app_number] => 9/257837 [patent_app_country] => US [patent_app_date] => 1999-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 6842 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/184/06184548.pdf [firstpage_image] =>[orig_patent_app_number] => 257837 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4401363 [patent_doc_number] => 06297537 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-02 [patent_title] => 'Semiconductor device and method for production thereof' [patent_app_type] => 1 [patent_app_number] => 9/253000 [patent_app_country] => US [patent_app_date] => 1999-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 18 [patent_no_of_words] => 4350 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/297/06297537.pdf [firstpage_image] =>[orig_patent_app_number] => 253000 [rel_patent_id] =>[rel_patent_doc_number] =>)