Search

Eric E. Silverman

Examiner (ID: 15411)

Most Active Art Unit
1618
Art Unit(s)
1618, 1615
Total Applications
298
Issued Applications
111
Pending Applications
2
Abandoned Applications
185

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 397575 [patent_doc_number] => 07294544 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-11-13 [patent_title] => 'Method of making a metal-insulator-metal capacitor in the CMOS process' [patent_app_type] => utility [patent_app_number] => 09/249254 [patent_app_country] => US [patent_app_date] => 1999-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2084 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/294/07294544.pdf [firstpage_image] =>[orig_patent_app_number] => 09249254 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/249254
Method of making a metal-insulator-metal capacitor in the CMOS process Feb 11, 1999 Issued
Array ( [id] => 4258750 [patent_doc_number] => 06258660 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-10 [patent_title] => 'Method of making a self-aligned recessed container cell capacitor' [patent_app_type] => 1 [patent_app_number] => 9/249388 [patent_app_country] => US [patent_app_date] => 1999-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 2896 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 23 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/258/06258660.pdf [firstpage_image] =>[orig_patent_app_number] => 249388 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/249388
Method of making a self-aligned recessed container cell capacitor Feb 11, 1999 Issued
Array ( [id] => 4357399 [patent_doc_number] => 06190987 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-20 [patent_title] => 'MOS semiconductor device and method of manufacturing the same' [patent_app_type] => 1 [patent_app_number] => 9/246799 [patent_app_country] => US [patent_app_date] => 1999-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 28 [patent_no_of_words] => 6982 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/190/06190987.pdf [firstpage_image] =>[orig_patent_app_number] => 246799 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/246799
MOS semiconductor device and method of manufacturing the same Feb 8, 1999 Issued
Array ( [id] => 4361053 [patent_doc_number] => 06218734 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-17 [patent_title] => 'Copper adhered to a diffusion barrier surface' [patent_app_type] => 1 [patent_app_number] => 9/247650 [patent_app_country] => US [patent_app_date] => 1999-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 4284 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/218/06218734.pdf [firstpage_image] =>[orig_patent_app_number] => 247650 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/247650
Copper adhered to a diffusion barrier surface Feb 8, 1999 Issued
Array ( [id] => 4408749 [patent_doc_number] => 06300237 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-09 [patent_title] => 'Semiconductor integrated circuit device and method for making the same' [patent_app_type] => 1 [patent_app_number] => 9/245743 [patent_app_country] => US [patent_app_date] => 1999-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 17 [patent_no_of_words] => 6301 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/300/06300237.pdf [firstpage_image] =>[orig_patent_app_number] => 245743 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/245743
Semiconductor integrated circuit device and method for making the same Feb 7, 1999 Issued
Array ( [id] => 4419163 [patent_doc_number] => 06177285 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-23 [patent_title] => 'Process for determining the crystal orientation in a wafer' [patent_app_type] => 1 [patent_app_number] => 9/142124 [patent_app_country] => US [patent_app_date] => 1999-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2196 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 264 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/177/06177285.pdf [firstpage_image] =>[orig_patent_app_number] => 142124 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/142124
Process for determining the crystal orientation in a wafer Feb 4, 1999 Issued
Array ( [id] => 4233568 [patent_doc_number] => 06074899 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-13 [patent_title] => '3-D CMOS-on-SOI ESD structure and method' [patent_app_type] => 1 [patent_app_number] => 9/245488 [patent_app_country] => US [patent_app_date] => 1999-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 5622 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/074/06074899.pdf [firstpage_image] =>[orig_patent_app_number] => 245488 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/245488
3-D CMOS-on-SOI ESD structure and method Feb 4, 1999 Issued
Array ( [id] => 4359062 [patent_doc_number] => 06291871 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-18 [patent_title] => 'Method of jointly forming stacked capacitors and antifuses, method of blowing antifuses, and antifuses and stacked capacitors constituting a part of integrated circuitry' [patent_app_type] => 1 [patent_app_number] => 9/244557 [patent_app_country] => US [patent_app_date] => 1999-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 15 [patent_no_of_words] => 2593 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/291/06291871.pdf [firstpage_image] =>[orig_patent_app_number] => 244557 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/244557
Method of jointly forming stacked capacitors and antifuses, method of blowing antifuses, and antifuses and stacked capacitors constituting a part of integrated circuitry Feb 2, 1999 Issued
Array ( [id] => 4274660 [patent_doc_number] => 06267479 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-31 [patent_title] => 'Semiconductor device, and method for manufacturing the same' [patent_app_type] => 1 [patent_app_number] => 9/241138 [patent_app_country] => US [patent_app_date] => 1999-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 47 [patent_figures_cnt] => 161 [patent_no_of_words] => 19496 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 260 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/267/06267479.pdf [firstpage_image] =>[orig_patent_app_number] => 241138 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/241138
Semiconductor device, and method for manufacturing the same Feb 1, 1999 Issued
Array ( [id] => 6290344 [patent_doc_number] => 20020055207 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-09 [patent_title] => 'METHOD FOR FABRICATING THIN-FILM TRANSISTOR' [patent_app_type] => new [patent_app_number] => 09/238899 [patent_app_country] => US [patent_app_date] => 1999-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6055 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0055/20020055207.pdf [firstpage_image] =>[orig_patent_app_number] => 09238899 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/238899
Method for fabricating thin-film transistor Jan 27, 1999 Issued
Array ( [id] => 4347511 [patent_doc_number] => 06214654 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-10 [patent_title] => 'Method for forming super-steep retrograded channel (SSRC) for CMOS transistor using rapid laser annealing to reduce thermal budget' [patent_app_type] => 1 [patent_app_number] => 9/238358 [patent_app_country] => US [patent_app_date] => 1999-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 2055 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/214/06214654.pdf [firstpage_image] =>[orig_patent_app_number] => 238358 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/238358
Method for forming super-steep retrograded channel (SSRC) for CMOS transistor using rapid laser annealing to reduce thermal budget Jan 26, 1999 Issued
Array ( [id] => 4158887 [patent_doc_number] => 06124614 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-26 [patent_title] => 'Si/SiGe MOSFET and method for fabricating the same' [patent_app_type] => 1 [patent_app_number] => 9/233329 [patent_app_country] => US [patent_app_date] => 1999-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 3304 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/124/06124614.pdf [firstpage_image] =>[orig_patent_app_number] => 233329 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/233329
Si/SiGe MOSFET and method for fabricating the same Jan 19, 1999 Issued
Array ( [id] => 4331275 [patent_doc_number] => 06329669 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-11 [patent_title] => 'Semiconductor device able to test changeover circuit which switches connection between terminals' [patent_app_type] => 1 [patent_app_number] => 9/233209 [patent_app_country] => US [patent_app_date] => 1999-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 19 [patent_no_of_words] => 9614 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/329/06329669.pdf [firstpage_image] =>[orig_patent_app_number] => 233209 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/233209
Semiconductor device able to test changeover circuit which switches connection between terminals Jan 19, 1999 Issued
Array ( [id] => 4270816 [patent_doc_number] => 06323071 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-27 [patent_title] => 'Method for forming a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/233146 [patent_app_country] => US [patent_app_date] => 1999-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 37 [patent_no_of_words] => 13073 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/323/06323071.pdf [firstpage_image] =>[orig_patent_app_number] => 233146 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/233146
Method for forming a semiconductor device Jan 18, 1999 Issued
Array ( [id] => 4258400 [patent_doc_number] => 06258636 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-10 [patent_title] => 'SOI active pixel cell design with grounded body contact' [patent_app_type] => 1 [patent_app_number] => 9/231068 [patent_app_country] => US [patent_app_date] => 1999-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 3945 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/258/06258636.pdf [firstpage_image] =>[orig_patent_app_number] => 231068 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/231068
SOI active pixel cell design with grounded body contact Jan 13, 1999 Issued
Array ( [id] => 4258964 [patent_doc_number] => 06258674 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-10 [patent_title] => 'High voltage field effect transistor and method of fabricating the same' [patent_app_type] => 1 [patent_app_number] => 9/231369 [patent_app_country] => US [patent_app_date] => 1999-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 20 [patent_no_of_words] => 3803 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/258/06258674.pdf [firstpage_image] =>[orig_patent_app_number] => 231369 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/231369
High voltage field effect transistor and method of fabricating the same Jan 12, 1999 Issued
Array ( [id] => 4317668 [patent_doc_number] => 06316794 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-13 [patent_title] => 'Lateral high voltage semiconductor device with protective silicon nitride film in voltage withstanding region' [patent_app_type] => 1 [patent_app_number] => 9/223668 [patent_app_country] => US [patent_app_date] => 1998-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 2896 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/316/06316794.pdf [firstpage_image] =>[orig_patent_app_number] => 223668 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/223668
Lateral high voltage semiconductor device with protective silicon nitride film in voltage withstanding region Dec 29, 1998 Issued
Array ( [id] => 4310534 [patent_doc_number] => 06252304 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-26 [patent_title] => 'Metallized vias with and method of fabrication' [patent_app_type] => 1 [patent_app_number] => 9/221967 [patent_app_country] => US [patent_app_date] => 1998-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2553 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/252/06252304.pdf [firstpage_image] =>[orig_patent_app_number] => 221967 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/221967
Metallized vias with and method of fabrication Dec 27, 1998 Issued
Array ( [id] => 4274970 [patent_doc_number] => 06281049 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-28 [patent_title] => 'Semiconductor device mask and method for forming the same' [patent_app_type] => 1 [patent_app_number] => 9/219528 [patent_app_country] => US [patent_app_date] => 1998-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 4531 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/281/06281049.pdf [firstpage_image] =>[orig_patent_app_number] => 219528 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/219528
Semiconductor device mask and method for forming the same Dec 22, 1998 Issued
Array ( [id] => 4410611 [patent_doc_number] => 06232618 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-15 [patent_title] => 'Sensor with temperature-dependent measuring resistor and its use for temperature measurement' [patent_app_type] => 1 [patent_app_number] => 9/218659 [patent_app_country] => US [patent_app_date] => 1998-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3431 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/232/06232618.pdf [firstpage_image] =>[orig_patent_app_number] => 218659 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/218659
Sensor with temperature-dependent measuring resistor and its use for temperature measurement Dec 21, 1998 Issued
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