Eric E. Silverman

Array ( [id] => 4218686 [patent_doc_number] => 06040206 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-21 [patent_title] => 'Thin film transistor' [patent_app_type] => 1 [patent_app_number] => 9/146428 [patent_app_country] => US [patent_app_date] => 1998-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 17 [patent_no_of_words] => 5567 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/040/06040206.pdf [firstpage_image] =>[orig_patent_app_number] => 146428 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4319517 [patent_doc_number] => 06242770 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-05 [patent_title] => 'Diode connected to a magnetic tunnel junction and self aligned with a metallic conductor and method for forming the same' [patent_app_type] => 1 [patent_app_number] => 9/144067 [patent_app_country] => US [patent_app_date] => 1998-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 21 [patent_no_of_words] => 5604 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/242/06242770.pdf [firstpage_image] =>[orig_patent_app_number] => 144067 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4293372 [patent_doc_number] => 06197624 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-06 [patent_title] => 'Method of adjusting the threshold voltage in an SOI CMOS' [patent_app_type] => 1 [patent_app_number] => 9/141778 [patent_app_country] => US [patent_app_date] => 1998-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 73 [patent_no_of_words] => 15116 [patent_no_of_claims] => 62 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/197/06197624.pdf [firstpage_image] =>[orig_patent_app_number] => 141778 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4326048 [patent_doc_number] => 06331723 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-18 [patent_title] => 'Active matrix display device having at least two transistors having LDD region in one pixel' [patent_app_type] => 1 [patent_app_number] => 9/137527 [patent_app_country] => US [patent_app_date] => 1998-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 38 [patent_no_of_words] => 8889 [patent_no_of_claims] => 124 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/331/06331723.pdf [firstpage_image] =>[orig_patent_app_number] => 137527 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4182981 [patent_doc_number] => 06159797 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-12 [patent_title] => 'Method of fabricating a flash memory with a planarized topography' [patent_app_type] => 1 [patent_app_number] => 9/137668 [patent_app_country] => US [patent_app_date] => 1998-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 1505 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/159/06159797.pdf [firstpage_image] =>[orig_patent_app_number] => 137668 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4401192 [patent_doc_number] => 06297525 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-02 [patent_title] => 'Capacitor structures, DRAM cell structures, and integrated circuitry' [patent_app_type] => 1 [patent_app_number] => 9/126979 [patent_app_country] => US [patent_app_date] => 1998-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 4501 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/297/06297525.pdf [firstpage_image] =>[orig_patent_app_number] => 126979 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4312543 [patent_doc_number] => 06242318 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-05 [patent_title] => 'Alignment method and semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/122793 [patent_app_country] => US [patent_app_date] => 1998-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 35 [patent_no_of_words] => 5761 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/242/06242318.pdf [firstpage_image] =>[orig_patent_app_number] => 122793 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4301634 [patent_doc_number] => 06251715 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-26 [patent_title] => 'Thin film transistor-liquid crystal display and a manufacturing method thereof' [patent_app_type] => 1 [patent_app_number] => 9/121911 [patent_app_country] => US [patent_app_date] => 1998-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 62 [patent_no_of_words] => 3068 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/251/06251715.pdf [firstpage_image] =>[orig_patent_app_number] => 121911 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1565673 [patent_doc_number] => 06376290 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-23 [patent_title] => 'Method of forming a semiconductor thin film on a plastic substrate' [patent_app_type] => B1 [patent_app_number] => 09/116119 [patent_app_country] => US [patent_app_date] => 1998-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 4269 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/376/06376290.pdf [firstpage_image] =>[orig_patent_app_number] => 09116119 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1071855 [patent_doc_number] => 06841439 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-01-11 [patent_title] => 'High permittivity silicate gate dielectric' [patent_app_type] => utility [patent_app_number] => 09/116138 [patent_app_country] => US [patent_app_date] => 1998-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 21 [patent_no_of_words] => 6135 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/841/06841439.pdf [firstpage_image] =>[orig_patent_app_number] => 09116138 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1561220 [patent_doc_number] => 06362097 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-26 [patent_title] => 'Collimated sputtering of semiconductor and other films' [patent_app_type] => B1 [patent_app_number] => 09/115258 [patent_app_country] => US [patent_app_date] => 1998-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 8347 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 15 [patent_words_short_claim] => 29 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/362/06362097.pdf [firstpage_image] =>[orig_patent_app_number] => 09115258 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4303170 [patent_doc_number] => 06326226 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-04 [patent_title] => 'Method of crystallizing an amorphous film' [patent_app_type] => 1 [patent_app_number] => 9/115498 [patent_app_country] => US [patent_app_date] => 1998-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 32 [patent_no_of_words] => 7413 [patent_no_of_claims] => 56 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/326/06326226.pdf [firstpage_image] =>[orig_patent_app_number] => 115498 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4254794 [patent_doc_number] => 06222250 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-24 [patent_title] => 'Bipolar transistor device and method for manufacturing the same' [patent_app_type] => 1 [patent_app_number] => 9/112230 [patent_app_country] => US [patent_app_date] => 1998-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 39 [patent_figures_cnt] => 39 [patent_no_of_words] => 10642 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 246 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/222/06222250.pdf [firstpage_image] =>[orig_patent_app_number] => 112230 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1587773 [patent_doc_number] => 06359301 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-19 [patent_title] => 'Semiconductor device and method of manufacturing the same' [patent_app_type] => B1 [patent_app_number] => 09/103618 [patent_app_country] => US [patent_app_date] => 1998-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 41 [patent_figures_cnt] => 41 [patent_no_of_words] => 9702 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/359/06359301.pdf [firstpage_image] =>[orig_patent_app_number] => 09103618 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4107538 [patent_doc_number] => 06057203 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-02 [patent_title] => 'Integrated circuit capacitor' [patent_app_type] => 1 [patent_app_number] => 9/099733 [patent_app_country] => US [patent_app_date] => 1998-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 9 [patent_no_of_words] => 1263 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/057/06057203.pdf [firstpage_image] =>[orig_patent_app_number] => 099733 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4404387 [patent_doc_number] => 06271062 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-07 [patent_title] => 'Thin film semiconductor device including a semiconductor film with high field-effect mobility' [patent_app_type] => 1 [patent_app_number] => 9/092509 [patent_app_country] => US [patent_app_date] => 1998-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 23 [patent_no_of_words] => 17759 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/271/06271062.pdf [firstpage_image] =>[orig_patent_app_number] => 092509 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1245734 [patent_doc_number] => 06677226 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-01-13 [patent_title] => 'Method for forming an integrated circuit having a bonding pad and a fuse' [patent_app_type] => B1 [patent_app_number] => 09/075767 [patent_app_country] => US [patent_app_date] => 1998-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 2234 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/677/06677226.pdf [firstpage_image] =>[orig_patent_app_number] => 09075767 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1101671 [patent_doc_number] => 06815303 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-11-09 [patent_title] => 'Bipolar transistors with low-resistance emitter contacts' [patent_app_type] => B2 [patent_app_number] => 09/069668 [patent_app_country] => US [patent_app_date] => 1998-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 2750 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/815/06815303.pdf [firstpage_image] =>[orig_patent_app_number] => 09069668 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4185427 [patent_doc_number] => 06093594 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-25 [patent_title] => 'CMOS optimization method utilizing sacrificial sidewall spacer' [patent_app_type] => 1 [patent_app_number] => 9/069879 [patent_app_country] => US [patent_app_date] => 1998-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 3496 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/093/06093594.pdf [firstpage_image] =>[orig_patent_app_number] => 069879 [rel_patent_id] =>[rel_patent_doc_number] =>)