Search

Eric E. Silverman

Examiner (ID: 15411)

Most Active Art Unit
1618
Art Unit(s)
1618, 1615
Total Applications
298
Issued Applications
111
Pending Applications
2
Abandoned Applications
185

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4204716 [patent_doc_number] => 06077743 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-20 [patent_title] => 'Method for making dynamic random access memory cells having brush-shaped stacked capacitors patterned from a hemispherical grain hard mask' [patent_app_type] => 1 [patent_app_number] => 9/066018 [patent_app_country] => US [patent_app_date] => 1998-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4817 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 456 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/077/06077743.pdf [firstpage_image] =>[orig_patent_app_number] => 066018 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/066018
Method for making dynamic random access memory cells having brush-shaped stacked capacitors patterned from a hemispherical grain hard mask Apr 23, 1998 Issued
Array ( [id] => 4204701 [patent_doc_number] => 06077742 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-20 [patent_title] => 'Method for making dynamic random access memory (DRAM) cells having zigzag-shaped stacked capacitors with increased capacitance' [patent_app_type] => 1 [patent_app_number] => 9/066017 [patent_app_country] => US [patent_app_date] => 1998-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5867 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 510 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/077/06077742.pdf [firstpage_image] =>[orig_patent_app_number] => 066017 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/066017
Method for making dynamic random access memory (DRAM) cells having zigzag-shaped stacked capacitors with increased capacitance Apr 23, 1998 Issued
Array ( [id] => 4237235 [patent_doc_number] => 06090681 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-18 [patent_title] => 'Method of forming an HSG capacitor layer via implantation' [patent_app_type] => 1 [patent_app_number] => 9/064067 [patent_app_country] => US [patent_app_date] => 1998-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 21 [patent_no_of_words] => 2682 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/090/06090681.pdf [firstpage_image] =>[orig_patent_app_number] => 064067 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/064067
Method of forming an HSG capacitor layer via implantation Apr 21, 1998 Issued
Array ( [id] => 4101286 [patent_doc_number] => 06100117 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-08 [patent_title] => 'Method for manufacturing DRAM having a redundancy circuit region' [patent_app_type] => 1 [patent_app_number] => 9/062639 [patent_app_country] => US [patent_app_date] => 1998-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 2079 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/100/06100117.pdf [firstpage_image] =>[orig_patent_app_number] => 062639 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/062639
Method for manufacturing DRAM having a redundancy circuit region Apr 19, 1998 Issued
Array ( [id] => 4238164 [patent_doc_number] => 06080633 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-27 [patent_title] => 'Method for manufacturing capacitor\'s lower electrode' [patent_app_type] => 1 [patent_app_number] => 9/061658 [patent_app_country] => US [patent_app_date] => 1998-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 2333 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 258 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/080/06080633.pdf [firstpage_image] =>[orig_patent_app_number] => 061658 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/061658
Method for manufacturing capacitor's lower electrode Apr 16, 1998 Issued
Array ( [id] => 4294028 [patent_doc_number] => 06211548 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-03 [patent_title] => 'Metal-gate non-volatile memory cell' [patent_app_type] => 1 [patent_app_number] => 9/062239 [patent_app_country] => US [patent_app_date] => 1998-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 22 [patent_no_of_words] => 4523 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/211/06211548.pdf [firstpage_image] =>[orig_patent_app_number] => 062239 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/062239
Metal-gate non-volatile memory cell Apr 16, 1998 Issued
Array ( [id] => 4214483 [patent_doc_number] => 06110786 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-29 [patent_title] => 'Semiconductor device having elevated gate electrode and elevated active regions and method of manufacture thereof' [patent_app_type] => 1 [patent_app_number] => 9/061409 [patent_app_country] => US [patent_app_date] => 1998-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 3441 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/110/06110786.pdf [firstpage_image] =>[orig_patent_app_number] => 061409 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/061409
Semiconductor device having elevated gate electrode and elevated active regions and method of manufacture thereof Apr 15, 1998 Issued
Array ( [id] => 4235410 [patent_doc_number] => 06143606 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-07 [patent_title] => 'Method for manufacturing split-gate flash memory cell' [patent_app_type] => 1 [patent_app_number] => 9/061618 [patent_app_country] => US [patent_app_date] => 1998-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 2542 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/143/06143606.pdf [firstpage_image] =>[orig_patent_app_number] => 061618 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/061618
Method for manufacturing split-gate flash memory cell Apr 15, 1998 Issued
Array ( [id] => 4101709 [patent_doc_number] => 06100147 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-08 [patent_title] => 'Method for manufacturing a high performance transistor with self-aligned dopant profile' [patent_app_type] => 1 [patent_app_number] => 9/061778 [patent_app_country] => US [patent_app_date] => 1998-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2470 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/100/06100147.pdf [firstpage_image] =>[orig_patent_app_number] => 061778 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/061778
Method for manufacturing a high performance transistor with self-aligned dopant profile Apr 15, 1998 Issued
Array ( [id] => 4145648 [patent_doc_number] => 06063670 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-16 [patent_title] => 'Gate fabrication processes for split-gate transistors' [patent_app_type] => 1 [patent_app_number] => 9/060919 [patent_app_country] => US [patent_app_date] => 1998-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 10 [patent_no_of_words] => 1962 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/063/06063670.pdf [firstpage_image] =>[orig_patent_app_number] => 060919 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/060919
Gate fabrication processes for split-gate transistors Apr 14, 1998 Issued
Array ( [id] => 4139333 [patent_doc_number] => 06060366 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-09 [patent_title] => 'Method for manufacturing dram capacitor incorporating liquid phase deposition' [patent_app_type] => 1 [patent_app_number] => 9/058579 [patent_app_country] => US [patent_app_date] => 1998-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2728 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/060/06060366.pdf [firstpage_image] =>[orig_patent_app_number] => 058579 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/058579
Method for manufacturing dram capacitor incorporating liquid phase deposition Apr 9, 1998 Issued
Array ( [id] => 4087005 [patent_doc_number] => 06133101 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-17 [patent_title] => 'Low mask count process to fabricate mask read only memory devices' [patent_app_type] => 1 [patent_app_number] => 9/057867 [patent_app_country] => US [patent_app_date] => 1998-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 2234 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 274 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/133/06133101.pdf [firstpage_image] =>[orig_patent_app_number] => 057867 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/057867
Low mask count process to fabricate mask read only memory devices Apr 8, 1998 Issued
Array ( [id] => 4189459 [patent_doc_number] => 06150701 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-21 [patent_title] => 'Insulative guard ring for a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/056618 [patent_app_country] => US [patent_app_date] => 1998-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3848 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/150/06150701.pdf [firstpage_image] =>[orig_patent_app_number] => 056618 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/056618
Insulative guard ring for a semiconductor device Apr 7, 1998 Issued
Array ( [id] => 4097743 [patent_doc_number] => 06048762 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-11 [patent_title] => 'Method of fabricating embedded dynamic random access memory' [patent_app_type] => 1 [patent_app_number] => 9/055577 [patent_app_country] => US [patent_app_date] => 1998-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 1224 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 267 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/048/06048762.pdf [firstpage_image] =>[orig_patent_app_number] => 055577 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/055577
Method of fabricating embedded dynamic random access memory Apr 5, 1998 Issued
Array ( [id] => 4169012 [patent_doc_number] => 06140180 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-31 [patent_title] => 'Method of fabricating storage capacitor for dynamic random-access memory' [patent_app_type] => 1 [patent_app_number] => 9/054837 [patent_app_country] => US [patent_app_date] => 1998-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2930 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 313 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/140/06140180.pdf [firstpage_image] =>[orig_patent_app_number] => 054837 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/054837
Method of fabricating storage capacitor for dynamic random-access memory Apr 2, 1998 Issued
Array ( [id] => 4181944 [patent_doc_number] => 06150200 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-21 [patent_title] => 'Semiconductor device and method of making' [patent_app_type] => 1 [patent_app_number] => 9/055119 [patent_app_country] => US [patent_app_date] => 1998-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 4001 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/150/06150200.pdf [firstpage_image] =>[orig_patent_app_number] => 055119 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/055119
Semiconductor device and method of making Apr 2, 1998 Issued
Array ( [id] => 4095182 [patent_doc_number] => 06096640 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-01 [patent_title] => 'Method of making a gate electrode stack with a diffusion barrier' [patent_app_type] => 1 [patent_app_number] => 9/054328 [patent_app_country] => US [patent_app_date] => 1998-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3047 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/096/06096640.pdf [firstpage_image] =>[orig_patent_app_number] => 054328 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/054328
Method of making a gate electrode stack with a diffusion barrier Apr 1, 1998 Issued
Array ( [id] => 1469768 [patent_doc_number] => 06406953 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-18 [patent_title] => 'Method for fabricating an integrated circuit with a transistor electrode' [patent_app_type] => B1 [patent_app_number] => 09/053557 [patent_app_country] => US [patent_app_date] => 1998-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 5249 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/406/06406953.pdf [firstpage_image] =>[orig_patent_app_number] => 09053557 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/053557
Method for fabricating an integrated circuit with a transistor electrode Mar 31, 1998 Issued
Array ( [id] => 4414172 [patent_doc_number] => 06229177 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-08 [patent_title] => 'Semiconductor with laterally non-uniform channel doping profile' [patent_app_type] => 1 [patent_app_number] => 9/050747 [patent_app_country] => US [patent_app_date] => 1998-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 2328 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/229/06229177.pdf [firstpage_image] =>[orig_patent_app_number] => 050747 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/050747
Semiconductor with laterally non-uniform channel doping profile Mar 29, 1998 Issued
Array ( [id] => 4424653 [patent_doc_number] => 06225659 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-01 [patent_title] => 'Trenched gate semiconductor device and method for low power applications' [patent_app_type] => 1 [patent_app_number] => 9/052058 [patent_app_country] => US [patent_app_date] => 1998-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 4154 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/225/06225659.pdf [firstpage_image] =>[orig_patent_app_number] => 052058 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/052058
Trenched gate semiconductor device and method for low power applications Mar 29, 1998 Issued
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