
Eric E. Silverman
Examiner (ID: 15411)
| Most Active Art Unit | 1618 |
| Art Unit(s) | 1618, 1615 |
| Total Applications | 298 |
| Issued Applications | 111 |
| Pending Applications | 2 |
| Abandoned Applications | 185 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4275009
[patent_doc_number] => 06307235
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-10-23
[patent_title] => 'Another technique for gated lateral bipolar transistors'
[patent_app_type] => 1
[patent_app_number] => 9/050728
[patent_app_country] => US
[patent_app_date] => 1998-03-30
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[pdf_file] => patents/06/307/06307235.pdf
[firstpage_image] =>[orig_patent_app_number] => 050728
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/050728 | Another technique for gated lateral bipolar transistors | Mar 29, 1998 | Issued |
Array
(
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[patent_doc_number] => 06121659
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[patent_issue_date] => 2000-09-19
[patent_title] => 'Buried patterned conductor planes for semiconductor-on-insulator integrated circuit'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/049488 | Buried patterned conductor planes for semiconductor-on-insulator integrated circuit | Mar 26, 1998 | Issued |
Array
(
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[patent_doc_number] => 06177330
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[patent_issue_date] => 2001-01-23
[patent_title] => 'Method for correcting alignment, method for manufacturing a semiconductor device and a semiconductor device'
[patent_app_type] => 1
[patent_app_number] => 9/048163
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[patent_app_date] => 1998-03-26
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Array
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[patent_issue_date] => 2000-11-21
[patent_title] => 'Method of fabricating semiconductor read-only memory device with reduced parastic capacitance between bit line and word line'
[patent_app_type] => 1
[patent_app_number] => 9/047228
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Array
(
[id] => 4359046
[patent_doc_number] => 06169011
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[patent_issue_date] => 2001-01-02
[patent_title] => 'Trench isolation structure and method for same'
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Array
(
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[patent_doc_number] => 06225650
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[patent_issue_date] => 2001-05-01
[patent_title] => 'GAN group crystal base member having low dislocation density, use thereof and manufacturing methods thereof'
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Array
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Array
(
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[patent_title] => 'Semiconductor device and manufacturing method thereof'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/046198 | Semiconductor device and manufacturing method thereof | Mar 22, 1998 | Issued |
Array
(
[id] => 4161502
[patent_doc_number] => 06107681
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[patent_issue_date] => 2000-08-22
[patent_title] => 'Pin-assignment method for integrated circuit packages to increase the electro-static discharge protective capability thereof'
[patent_app_type] => 1
[patent_app_number] => 9/045327
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/045327 | Pin-assignment method for integrated circuit packages to increase the electro-static discharge protective capability thereof | Mar 19, 1998 | Issued |
Array
(
[id] => 4385185
[patent_doc_number] => 06303942
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[patent_issue_date] => 2001-10-16
[patent_title] => 'Multi-layer charge injection barrier and uses thereof'
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[patent_app_number] => 9/042974
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[patent_app_date] => 1998-03-17
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/042974 | Multi-layer charge injection barrier and uses thereof | Mar 16, 1998 | Issued |
Array
(
[id] => 4258582
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Array
(
[id] => 4098015
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Array
(
[id] => 3943186
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Array
(
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Array
(
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Array
(
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Array
(
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Array
(
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Array
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Array
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