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Eric E. Silverman

Examiner (ID: 15411)

Most Active Art Unit
1618
Art Unit(s)
1618, 1615
Total Applications
298
Issued Applications
111
Pending Applications
2
Abandoned Applications
185

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3931946 [patent_doc_number] => 05952705 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-14 [patent_title] => 'Monolithically integrated planar semi-conductor arrangement with temperature compensation' [patent_app_type] => 1 [patent_app_number] => 8/981985 [patent_app_country] => US [patent_app_date] => 1998-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 2798 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/952/05952705.pdf [firstpage_image] =>[orig_patent_app_number] => 981985 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/981985
Monolithically integrated planar semi-conductor arrangement with temperature compensation Jan 8, 1998 Issued
Array ( [id] => 3943175 [patent_doc_number] => 05976907 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-02 [patent_title] => 'Solid state imaging device and production method for the same' [patent_app_type] => 1 [patent_app_number] => 9/005048 [patent_app_country] => US [patent_app_date] => 1998-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 4750 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/976/05976907.pdf [firstpage_image] =>[orig_patent_app_number] => 005048 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/005048
Solid state imaging device and production method for the same Jan 8, 1998 Issued
Array ( [id] => 4186142 [patent_doc_number] => 06093641 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-25 [patent_title] => 'Method for fabricating semiconductor device with an increased process tolerance' [patent_app_type] => 1 [patent_app_number] => 9/005229 [patent_app_country] => US [patent_app_date] => 1998-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 20 [patent_no_of_words] => 2252 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/093/06093641.pdf [firstpage_image] =>[orig_patent_app_number] => 005229 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/005229
Method for fabricating semiconductor device with an increased process tolerance Jan 8, 1998 Issued
09/004278 THIN FILM TRANSISTOR AND METHOD FOR FABRICATING THE SAME Jan 7, 1998 Issued
Array ( [id] => 4016700 [patent_doc_number] => 05924001 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-13 [patent_title] => 'Ion implantation for preventing polycide void' [patent_app_type] => 1 [patent_app_number] => 9/004188 [patent_app_country] => US [patent_app_date] => 1998-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 1972 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/924/05924001.pdf [firstpage_image] =>[orig_patent_app_number] => 004188 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/004188
Ion implantation for preventing polycide void Jan 7, 1998 Issued
09/004429 SOI ACTIVE PIXEL CELL DESIGN WITH GROUNDED BODY CONTACT Jan 7, 1998 Issued
Array ( [id] => 4102137 [patent_doc_number] => 06051452 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-18 [patent_title] => 'Method for manufacturing a semiconductor device with ion implantation' [patent_app_type] => 1 [patent_app_number] => 9/003339 [patent_app_country] => US [patent_app_date] => 1998-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 55 [patent_no_of_words] => 10317 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/051/06051452.pdf [firstpage_image] =>[orig_patent_app_number] => 003339 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/003339
Method for manufacturing a semiconductor device with ion implantation Jan 5, 1998 Issued
09/002998 INTEGRATED CMOS TRANSISTOR FORMATION Jan 4, 1998 Abandoned
Array ( [id] => 4113952 [patent_doc_number] => 06046089 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-04 [patent_title] => 'Selectively sized spacers' [patent_app_type] => 1 [patent_app_number] => 9/002727 [patent_app_country] => US [patent_app_date] => 1998-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 2765 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/046/06046089.pdf [firstpage_image] =>[orig_patent_app_number] => 002727 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/002727
Selectively sized spacers Jan 4, 1998 Issued
Array ( [id] => 4237900 [patent_doc_number] => 06080615 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-27 [patent_title] => 'Method for forming a semiconductor device incorporating a dummy gate electrode' [patent_app_type] => 1 [patent_app_number] => 9/002679 [patent_app_country] => US [patent_app_date] => 1998-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 19 [patent_no_of_words] => 2178 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/080/06080615.pdf [firstpage_image] =>[orig_patent_app_number] => 002679 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/002679
Method for forming a semiconductor device incorporating a dummy gate electrode Jan 4, 1998 Issued
Array ( [id] => 3943428 [patent_doc_number] => 05976924 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-02 [patent_title] => 'Method of making a self-aligned disposable gate electrode for advanced CMOS design' [patent_app_type] => 1 [patent_app_number] => 9/000599 [patent_app_country] => US [patent_app_date] => 1997-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 3791 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/976/05976924.pdf [firstpage_image] =>[orig_patent_app_number] => 000599 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/000599
Method of making a self-aligned disposable gate electrode for advanced CMOS design Dec 29, 1997 Issued
08/998048 HIGH VOLTAGE THIN FILM TRANSISTOR WITH IMPROVED ON-STATE CHARACTERISTICS AND METHOD FOR MAKING SAME Dec 23, 1997 Abandoned
Array ( [id] => 4016247 [patent_doc_number] => 05923969 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-13 [patent_title] => 'Method for manufacturing a semiconductor device having a limited pocket region' [patent_app_type] => 1 [patent_app_number] => 8/997888 [patent_app_country] => US [patent_app_date] => 1997-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 34 [patent_no_of_words] => 7490 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/923/05923969.pdf [firstpage_image] =>[orig_patent_app_number] => 997888 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/997888
Method for manufacturing a semiconductor device having a limited pocket region Dec 23, 1997 Issued
Array ( [id] => 4155084 [patent_doc_number] => 06114200 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-05 [patent_title] => 'Method of fabricating a dynamic random access memory device' [patent_app_type] => 1 [patent_app_number] => 8/996697 [patent_app_country] => US [patent_app_date] => 1997-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 1720 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/114/06114200.pdf [firstpage_image] =>[orig_patent_app_number] => 996697 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/996697
Method of fabricating a dynamic random access memory device Dec 22, 1997 Issued
Array ( [id] => 4064257 [patent_doc_number] => 06008115 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-28 [patent_title] => 'Method for forming structure of wires for a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/997587 [patent_app_country] => US [patent_app_date] => 1997-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 2240 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/008/06008115.pdf [firstpage_image] =>[orig_patent_app_number] => 997587 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/997587
Method for forming structure of wires for a semiconductor device Dec 22, 1997 Issued
Array ( [id] => 4139373 [patent_doc_number] => 06060369 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-09 [patent_title] => 'Nitrogen bearing sacrificial oxide with subsequent high nitrogen dopant profile for high performance MOSFET' [patent_app_type] => 1 [patent_app_number] => 8/997318 [patent_app_country] => US [patent_app_date] => 1997-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 8 [patent_no_of_words] => 3748 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/060/06060369.pdf [firstpage_image] =>[orig_patent_app_number] => 997318 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/997318
Nitrogen bearing sacrificial oxide with subsequent high nitrogen dopant profile for high performance MOSFET Dec 22, 1997 Issued
Array ( [id] => 4215149 [patent_doc_number] => 06087215 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-11 [patent_title] => 'Method of fabricating a DRAM device' [patent_app_type] => 1 [patent_app_number] => 8/996018 [patent_app_country] => US [patent_app_date] => 1997-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 3256 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/087/06087215.pdf [firstpage_image] =>[orig_patent_app_number] => 996018 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/996018
Method of fabricating a DRAM device Dec 21, 1997 Issued
Array ( [id] => 3937045 [patent_doc_number] => 05915188 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-22 [patent_title] => 'Integrated inductor and capacitor on a substrate and method for fabricating same' [patent_app_type] => 1 [patent_app_number] => 8/996228 [patent_app_country] => US [patent_app_date] => 1997-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 1693 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/915/05915188.pdf [firstpage_image] =>[orig_patent_app_number] => 996228 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/996228
Integrated inductor and capacitor on a substrate and method for fabricating same Dec 21, 1997 Issued
Array ( [id] => 1192879 [patent_doc_number] => 06730528 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-05-04 [patent_title] => 'Mask set for measuring an overlapping error and method of measuring an overlapping error using the same' [patent_app_type] => B1 [patent_app_number] => 08/999401 [patent_app_country] => US [patent_app_date] => 1997-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 1833 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/730/06730528.pdf [firstpage_image] =>[orig_patent_app_number] => 08999401 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/999401
Mask set for measuring an overlapping error and method of measuring an overlapping error using the same Dec 21, 1997 Issued
Array ( [id] => 4181318 [patent_doc_number] => 06020241 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-01 [patent_title] => 'Post metal code engineering for a ROM' [patent_app_type] => 1 [patent_app_number] => 8/995338 [patent_app_country] => US [patent_app_date] => 1997-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 17 [patent_no_of_words] => 5843 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 252 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/020/06020241.pdf [firstpage_image] =>[orig_patent_app_number] => 995338 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/995338
Post metal code engineering for a ROM Dec 21, 1997 Issued
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